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1. 发明授权

US07660968B2 Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins 有权
标题翻译：可重构接口，用于将功能输入/输出块耦合到有限数量的I / O引脚
公开(公告)号：US07660968B2
公开(公告)日：2010-02-09
申请号：US11772184
申请日：2007-06-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.
摘要翻译：可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。该功能包括作为输入的功能的输出，功能定义的功能。每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

2. 发明授权

US07171542B1 Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins 失效
标题翻译：用于将功能输入/输出块耦合到有限数量的I / O引脚的可重新配置的接口
公开(公告)号：US07171542B1
公开(公告)日：2007-01-30
申请号：US09885459
申请日：2001-06-19
申请人： Donald E. Alfano , Danny Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R Holberg
发明人： Donald E. Alfano , Danny Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R Holberg
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.
摘要翻译：集成电路中的可重构处理器系统包括对一组指令进行操作以执行预定义的处理的处理器核心。提供多个输入/输出引脚用于与外部信号进行接口。可重新配置的接口通过多个功能块中的选择的接口在处理器核心和输入/输出引脚之间进行接口。可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心与处理器核心相连接的功能。功能块提供处理器内核与输入/输出引脚的接口。

3. 发明授权

US07504900B2 Integrated circuit package including programmable oscillators 有权
标题翻译：集成电路封装，包括可编程振荡器
公开(公告)号：US07504900B2
公开(公告)日：2009-03-17
申请号：US11694624
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F1/04 , H03B5/00 , H03B5/12 , H03B5/24 , H03B5/36
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.
摘要翻译：集成电路封装包括处理核心和内部振荡器。处理核心通过一组指令来执行预定义的过程。内部振荡器为集成电路封装提供系统时钟。内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

4. 发明授权

US07498962B2 Analog-to-digital converter with low power track-and-hold mode 有权
标题翻译：具有低功率跟踪和保持模式的模数转换器
公开(公告)号：US07498962B2
公开(公告)日：2009-03-03
申请号：US11618644
申请日：2006-12-29
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： H03M1/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.
摘要翻译：一种将模拟数据转换为数字数据的方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式将采样后的采样输入信号转换为数字信号。模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

5. 发明授权

US07492139B2 Digital control circuit for switching power supply with serial data input 有权
标题翻译：数字控制电路，用于串行数据输入开关电源
公开(公告)号：US07492139B2
公开(公告)日：2009-02-17
申请号：US11382462
申请日：2006-05-09
申请人： Donald E. Alfano , Paul Highley , Kenneth W. Fernald
发明人： Donald E. Alfano , Paul Highley , Kenneth W. Fernald
IPC分类号： G05F1/40
CPC分类号： H02M3/33576 , H02M3/33515
摘要： A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. The method includes switching current in a switching operation from the input to the output through an inductive element and measuring the voltage/current parameters on the input and output. A control algorithm is then utilized to determine control parameters necessary to make a control move to effect the switching operation, the control algorithm utilizing as inputs the measured voltage/current parameters. A digital control system controls the switching operation, which digital control system is operable to be controlled by the control algorithm. Configuration data is received on a serial data bus for configuring the control algorithm. Thereafter, the operation of the control algorithm is modified in response to receiving the configuration information.
摘要翻译：公开了一种用于将DC功率从输入端的第一电压电平转换为输出到输出的输出上的不同电压电平的方法。该方法包括通过电感元件将开关操作中的电流从输入切换到输出，并测量输入和输出上的电压/电流参数。然后利用控制算法来确定使控制移动以实现开关操作所必需的控制参数，该控制算法利用测量的电压/电流参数作为输入。数字控制系统控制切换操作，数字控制系统可操作地由控制算法控制。在串行数据总线上接收配置数据，以配置控制算法。此后，响应于接收到配置信息来修改控制算法的操作。

6. 发明授权

US07613901B2 Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation 有权
标题翻译： IC中的比较器具有可编程控制的正/负滞后电平和开漏/推挽输出，连接到交叉开关或上升/下降沿中断产生
公开(公告)号：US07613901B2
公开(公告)日：2009-11-03
申请号：US11694629
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F19/00 , H03K5/22
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.
摘要翻译：集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。多个比较器执行集成电路封装内的比较操作。至少一个控制寄存器与多个比较器中的每个比较器相关联，并且多个比较器中的每一个可软件编程以响应于通过处理在比较器的至少一个控制寄存器中建立的控制位来控制比较器的滞后核心。通过第一组控制位来编程正滞后量，经由第二组控制位来编程负滞后量。

7. 发明授权

US07042201B2 Digital control circuit for switching power supply with pattern generator 失效
标题翻译：用模式发生器切换电源的数字控制电路
公开(公告)号：US07042201B2
公开(公告)日：2006-05-09
申请号：US10742509
申请日：2003-12-19
申请人： Donald E. Alfano , Paul Highley , Kenneth W. Fernald
发明人： Donald E. Alfano , Paul Highley , Kenneth W. Fernald
IPC分类号： G05F1/40
CPC分类号： H02M3/33576 , H02M3/33515
摘要： Digital control circuit for switching power supply with pattern generator. A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. Current from the input is switched to the output through an inductive element with a plurality of switches, each of the switches driven by a waveform, all of the waveforms driving the switches referenced with a predetermined relationship to a master clock and all operating on a PWM duty cycle of the master clock. The voltage/current parameters on the input and output are measured and then a control algorithm is utilized to determine a change in the PWM duty cycle necessary to make a control move, the control algorithm utilizing as inputs the measured voltage/current parameters. A pre-stored waveform pattern for each of the waveforms is then modified to reflect the change in the PWM duty cycle required for the control move. After modification, the modified pattern is output to create the waveform and drive the respective switches.
摘要翻译：用模式发生器切换电源的数字控制电路。公开了一种用于将DC功率从输入端的第一电压电平转换为输出到输出的输出上的不同电压电平的方法。来自输入的电流通过具有多个开关的电感元件切换到输出，每个开关由波形驱动，驱动开关的所有波形以与主时钟预定的关系为参考，并且全部在PWM上工作主时钟的占空比。测量输入和输出上的电压/电流参数，然后使用控制算法来确定进行控制移动所需的PWM占空比的变化，该控制算法利用测量的电压/电流参数作为输入。然后对每个波形的预先存储的波形图进行修改，以反映控制移动所需的PWM占空比的变化。修改后，输出修改后的图案，创建波形并驱动各个开关。

8. 发明授权

US06839795B1 Priority cross-bar decoder 有权
标题翻译：优先交叉条解码器
公开(公告)号：US06839795B1
公开(公告)日：2005-01-04
申请号：US09584308
申请日：2000-05-31
申请人： Kenneth W. Fernald , Danny J. Allred , Donald E. Alfano
发明人： Kenneth W. Fernald , Danny J. Allred , Donald E. Alfano
IPC分类号： H04Q3/52 , G06F13/00
CPC分类号： H04Q3/52 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/1325
摘要： A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used. The outputs of the cross-bar decoder (70) are coupled to respective I/O pins (170, 172, 174) by way of respective driver circuits (212, 216, 236).
摘要翻译：形成交叉条形码解码器（70）的路由信元的矩阵。耦合到交叉条形码解码器（70）的信号三元组（84,86,88）被赋予优先权。寄存器（50）向交叉条形码解码器（70）提供输出以通过交叉条形码解码器（70）来激活或去激活三联信号（84,88,88）的路由。路由单元（72-82）被布置成列和行的矩阵，其中三元组信号被施加到行路由单元（72,74,76），并且在列路由单元（76,80,82）处被提取）。当一行中的路由单元被使能以将信号耦合到输出时，它将禁用其列中的所有其他较低优先级的路由单元，使得它们不能将信号路由到该输出。基于其他路由单元的自动禁用，通过交叉条形码解码器（70）的信号直到所有高优先级I / O引脚使用。横杆解码器（70）的输出通过相应的驱动器电路（212,216,236）耦合到相应的I / O引脚（170,172,174）。

9. 发明授权

US07343504B2 Micro controller unit (MCU) with RTC 有权
标题翻译：微控制器（MCU）与RTC
公开(公告)号：US07343504B2
公开(公告)日：2008-03-11
申请号：US10881793
申请日：2004-06-30
申请人： Kenneth W. Fernald , Donald E. Alfano
发明人： Kenneth W. Fernald , Donald E. Alfano
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand-alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer. A power management circuitry manages the power to the stand-alone RTC circuit, such that the RTC clock circuit, the timer, and the I/O device operate regardless of the power mode of operation of the processing circuitry and the primary clock circuit.
摘要翻译：公开了具有独立实时时钟（RTC）的微控制器单元（MCU）。 MCU包括用于接收数字信息并处理所接收的数字信息的处理电路。主时钟电路为处理电路提供定时。电源控制电路控制处理电路和主时钟电路的电源，以控制其工作在至少全功率模式下工作，从供电电压输入和低功耗模式绘制小于全功率模式功率电平从电源电压输入。还提供独立的RTC电路，独立的RTC电路包括独立于主时钟电路工作的RTC时钟电路。由RTC时钟电路计时钟的定时器可操作以增加存储的时间值以便从其输出，RTC时钟电路具有确定的时基。输入/输出（I / O）设备提供处理电路对定时器输出的结果的访问。电源管理电路管理独立RTC电路的电源，使得RTC时钟电路，定时器和I / O设备无论处理电路和主时钟电路的功率工作模式如何都工作。

10. 发明授权

US07071733B2 Cross-bar matrix for connecting digital resources to I/O pins of an integrated circuit 有权
标题翻译：用于将数字资源连接到集成电路的I / O引脚的交叉矩阵
公开(公告)号：US07071733B2
公开(公告)日：2006-07-04
申请号：US10847632
申请日：2004-05-17
申请人： Kenneth W. Fernald , Donald E. Alfano
发明人： Kenneth W. Fernald , Donald E. Alfano
IPC分类号： H03K19/177
CPC分类号： H04Q3/52 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/1325
摘要： A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.
摘要翻译：形成交叉条形码解码器（310）的路由信元的矩阵。基于微处理器的控制，信号三元组通过交叉条形码解码器（310）耦合。寄存器（50）向跨栏解码器（310）提供控制信号，以通过交叉条形码解码器（310）的单元激活或去激活三联信号的路由。路由单元被排列成列和行的矩阵。每行单元格与公共数据信号输入相关联，矩阵的每一列与一个公共I / O引脚相关联。这些单元由微处理器单独使能，以便任何数据信号可以耦合到任何I / O引脚。除了通过单元格路由数据信号之外，其他信号也通过单元进行路由。

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