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1. 发明授权

US06924952B1 Method and apparatus for data storage in a disk drive 有权
标题翻译：数据存储在磁盘驱动器中的方法和装置
公开(公告)号：US06924952B1
公开(公告)日：2005-08-02
申请号：US09923910
申请日：2001-08-06
申请人： Don Brunnett , Uwe Schwiegelshohn , Steve McCarthy
发明人： Don Brunnett , Uwe Schwiegelshohn , Steve McCarthy
IPC分类号： G06F3/06 , G11B5/09 , G11B20/10 , G11B20/12 , G11B27/36
CPC分类号： G06F3/0619 , G06F3/064 , G06F3/0674 , G11B5/09 , G11B20/10 , G11B20/1252 , G11B27/36 , G11B2020/1222 , G11B2020/1232 , G11B2220/20 , G11B2220/2516
摘要： A method and apparatus for increasing formatting efficiency of a disk drive is disclosed. In one embodiment, a method for storing data in a disk drive is provided. The disk drive is coupled to a computer via an interface. The method includes the steps of storing data on a disk surface in a disk block having a predetermined length; and, presenting data from the disk drive to the interface as a host block having a predetermined length, wherein the predetermined length of the disk block is equal to N times the predetermined length of the host block, where N is a natural number greater than 1. In one embodiment, a read/modify/write procedure is provided to ensure that data is not lost when a power failure occurs during a write operation when the number of host blocks being written is not a multiple of N.
摘要翻译：公开了一种用于提高磁盘驱动器的格式化效率的方法和装置。在一个实施例中，提供了一种用于将数据存储在磁盘驱动器中的方法。磁盘驱动器经由接口耦合到计算机。该方法包括以下步骤：将数据存储在具有预定长度的盘块中的盘表面上; 并且将来自磁盘驱动器的数据呈现为具有预定长度的主机块的接口，其中盘块的预定长度等于主机块的预定长度的N倍，其中N是大于1的自然数在一个实施例中，提供读/修改/写入过程以确保在写入操作期间发生电源故障时数据不会丢失，当正在写入的主机块的数量不是N的倍数时。

2. 发明授权

US5687375A Debugging of High Performance Fortran programs with backup breakpoints 失效
标题翻译：使用备份断点调试高性能Fortran程序
公开(公告)号：US5687375A
公开(公告)日：1997-11-11
申请号：US323415
申请日：1994-10-14
申请人： Uwe Schwiegelshohn
发明人： Uwe Schwiegelshohn
IPC分类号： G06F11/36 , G06F11/00
CPC分类号： G06F11/362
摘要： This invention is a debugger for HPF-like languages which can be implemented on top of basically any debugger. A primary feature of the debugger is the use of backup breakpoints to generate a program status which is similar to a program status in a sequential execution of the code and the back and forth mapping between processor variables. This debugger requires some new debugging information which must be provided by the compiler. It then allows debugging from a sequential point of view.
摘要翻译：本发明是用于类似HPF的语言的调试器，其可以在基本上任何调试器之上实现。调试器的主要特征是使用备份断点来生成程序状态，该程序状态与代码的顺序执行中的程序状态以及处理器变量之间的前后映射相似。这个调试器需要一些必须由编译器提供的调试信息。然后允许从连续的角度进行调试。

3. 发明授权

US5428628A Modular implementation for a parallelized key equation solver for linear algebraic codes 失效
标题翻译：用于线性代数代码的并行化关键方程求解器的模块化实现
公开(公告)号：US5428628A
公开(公告)日：1995-06-27
申请号：US127465
申请日：1993-09-27
申请人： Martin Hassner , Uwe Schwiegelshohn , Shmuel Winograd
发明人： Martin Hassner , Uwe Schwiegelshohn , Shmuel Winograd
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15
CPC分类号： H03M13/151
摘要： Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. Circuitry implements two computation sequences. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two sequences being required to decode t symbols in error. These sequences are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in the other sequence being paired with a multiplication operation in the next iteration of the one sequence. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed. Two consecutive executions of the other sequence are prevented.
摘要翻译：用于实现用于解码线性代数码的解码的关键方程的并行算法的装置和方法。电路实现两个计算序列。其中一个执行三个乘法运算，另一个执行五个乘法运算，需要这两个序列的2t次迭代来解码错误的t个符号。这些序列被耦合，使得在每个连续的2t迭代期间，四个乘法运算被成对同时执行，另一个序列中的第五次乘法运算与在一个序列的下一次迭代中的乘法运算配对。在一对配对乘法运算中，执行逆表查找操作，而在另一乘法运算期间，执行加法运算。防止其他顺序的两个连续执行。

4. 发明授权

US5384567A Combination parallel/serial execution of sequential algorithm for data compression/decompression 失效
标题翻译：组合并行/串行执行数据压缩/解压缩的顺序算法
公开(公告)号：US5384567A
公开(公告)日：1995-01-24
申请号：US89211
申请日：1993-07-08
申请人： Martin A. Hassner , Ehud D. Karnin , Uwe Schwiegelshohn , Tetsuya Tamura
发明人： Martin A. Hassner , Ehud D. Karnin , Uwe Schwiegelshohn , Tetsuya Tamura
IPC分类号： G06F5/00 , G06T9/00 , H03M7/30 , H04B1/66
CPC分类号： H03M7/3086 , G06T9/005
摘要： An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer compresses an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
摘要翻译：一种用于执行顺序数据压缩算法的装置和方法，其特别适用于在设备（与主机不同）控制器中需要数据压缩的地方。历史缓冲区压缩i个相同水平切片单元的阵列。每个片单元存储j个符号以定义其中每个片单元中的符号被精确地i个符号分隔的j个分离块。 i个输入符号的串中的符号被i个比较器与先前存储在片单元中的符号并行地进行比较，以识别符号的匹配序列。控制单元控制顺序算法的执行，以使比较器平行扫描符号，但在每个块中顺序扫描符号，并使符号的匹配序列和非匹配序列存储在阵列中。选择参数i和j以限制在基于算法执行速度与硬件成本的折衷来执行算法时实现期望的效率程度所需的比较器的数量。优先编码器根据由片单元输出的信号计算每个j，i地址，其中标识匹配序列，但是它输出这些地址中只有一个（例如最小的）的地址。

5. 发明授权

US5594436A Signal processing channel with high data rate and low power consumption 失效
标题翻译：具有高数据速率和低功耗的信号处理通道
公开(公告)号：US5594436A
公开(公告)日：1997-01-14
申请号：US327062
申请日：1994-10-21
申请人： Martin A. Hassner , Uwe Schwiegelshohn , Shmuel Winograd
发明人： Martin A. Hassner , Uwe Schwiegelshohn , Shmuel Winograd
IPC分类号： G11B20/10 , G11B20/14 , H03M7/00
CPC分类号： G11B20/10 , G11B20/1426
摘要： An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n>1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.
摘要翻译：一种用于检测表示从数据存储装置读取的n位RLL编码数据的模式的模拟信号的装置和方法。 R个积分器每个在连续的时间段上对模拟信号进行积分，该连续的时间段由一个预选的n个位循环组成，其中n≥1，由n个正交信号的预选集合加权，n个正交信号是阶梯函数，它们改变每个位周期以提供R个积分加权输出。 R集成加权输出由查找表或只读存储器转换成对应于n位模拟数据模式中的唯一一个的n位数字表示。

6. 发明授权

US5444719A Adjustable error-correction composite Reed-Solomon encoder/syndrome generator 失效
标题翻译：可纠正的纠错复合Reed-Solomon编码器/综合发生器
公开(公告)号：US5444719A
公开(公告)日：1995-08-22
申请号：US8922
申请日：1993-01-26
申请人： Charles E. Cox , Gerhard P. Fettweis , Martin A. Hassner , Uwe Schwiegelshohn
发明人： Charles E. Cox , Gerhard P. Fettweis , Martin A. Hassner , Uwe Schwiegelshohn
IPC分类号： G06F11/10 , G11B20/18 , H03M13/00 , H03M13/15 , H03M13/35
CPC分类号： G11B20/1833 , H03M13/151 , H03M13/35
摘要： A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.
摘要翻译：复合编码器/校正子产生电路使用具有变化的抽头权重的单组乘法器装置来计算校验符号和误差校正子，所述抽头权重具有提供最大预选误差校正能力但容易调节的值，例如通过可编程锁存器，以从电路选择乘法器设备，以减少纠错能力，而不需要抽头重量值的变化。电路可以用于增加或减少纠错能力（a），根据在带状直接存取数据存储装置中正在访问多个记录磁道的同心磁带中的哪一个，（b）根据在数据通信信道具有受噪声的输出，或（c）根据以可变速率发送数据的发送设备的发送速率的变化。

7. 发明授权

US5487077A Location dependent variable error correction processing for multi-track recording media using variable length coding means 失效
标题翻译：使用可变长度编码装置的多轨记录介质的位置相关变量纠错处理
公开(公告)号：US5487077A
公开(公告)日：1996-01-23
申请号：US247446
申请日：1994-05-23
申请人： Martin A. Hassner , Luke C. K. Lang , Norman K. Ouchi , Uwe Schwiegelshohn
发明人： Martin A. Hassner , Luke C. K. Lang , Norman K. Ouchi , Uwe Schwiegelshohn
IPC分类号： G11B20/12 , G11B20/18 , H03M13/35 , G06F11/10
CPC分类号： H03M13/35 , G11B20/1833 , G11B20/1258
摘要： The error correction code capability of the linear recording density of a zone of contiguous recording tracks on a surface or volume having at lest two zones of different average linear recording density is adjusted. Each zone has associated therewith a parameter pair (r,R) defining the number of error correction bytes r to be appended to data blocks to form a codeword written to tracks within the zone and the number R.ltoreq.(r/2-1) of correctable errors in the event of a non-zero remainder detected upon readback of a codeword from a track within the zone. The r parameter controls the length of a shift register type encoder syndrome generator.
摘要翻译：在具有不同平均线性记录密度的两个区域的表面或体积上的连续记录轨迹区域的线性记录密度的纠错码能力被调整。每个区域具有与其相关联的参数对（r，R），其定义要附加到数据块的纠错字节数r，以形成写入该区域内的轨道的码字，并且数量R（r / 2-1 ）在从区域内的轨道读取码字时检测到非零余数的情况下的可校正错误。 r参数控制移位寄存器型编码器校正发生器的长度。

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