专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08874051B2 Systems and methods for power control in a multiple standard mobile transmitter 有权
标题翻译：多标准移动发射机功率控制系统和方法
公开(公告)号：US08874051B2
公开(公告)日：2014-10-28
申请号：US13310434
申请日：2011-12-02
申请人： Dmitriy Rozenblit , Masoud Kahrizi , Jaleh Komaili , Rajasekhar Pullela , Shahrzad Tadjpour
发明人： Dmitriy Rozenblit , Masoud Kahrizi , Jaleh Komaili , Rajasekhar Pullela , Shahrzad Tadjpour
IPC分类号： H04B1/04 , H03G3/30
CPC分类号： H04L1/0033 , H03F1/0211 , H03F3/19 , H03F3/195 , H03F3/21 , H03F3/245 , H03F2200/451 , H03F2200/465 , H03G3/3042
摘要： A transmitter adjusts a transmitted power level by modifying a control input of a variable gain amplifier. A power amplifier control system includes an envelope extractor, an error extractor, and a feed-forward multiplier. The envelope extractor receives data signal inputs and computes the envelope of the combined signal. The error extractor generates an error signal as a function of the combined signal and the output power generated by the power amplifier. The feed-forward multiplier generates a modified error signal that is responsive to a function of the gain in a feedback path. A corresponding method for controlling a power level is also disclosed. In some embodiments, a transmit chain with a power control loop is used to adjust the transmit signal power applied at an input of a variable gain amplifier. A corresponding method for adjusting the transmit signal power level is also included.
摘要翻译：发射机通过修改可变增益放大器的控制输入来调整发射功率电平。功率放大器控制系统包括信封提取器，误差提取器和前馈乘法器。信封提取器接收数据信号输入并计算组合信号的包络。误差提取器产生作为组合信号和功率放大器产生的输出功率的函数的误差信号。前馈乘法器产生响应于反馈路径中的增益的函数的修改的误差信号。还公开了一种用于控制功率电平的相应方法。在一些实施例中，具有功率控制环路的发射链用于调整在可变增益放大器的输入处施加的发射信号功率。还包括用于调整发射信号功率电平的相应方法。

2. 发明申请

US20120170624A1 SYSTEMS AND METHODS FOR POWER CONTROL IN A MULTIPLE STANDARD MOBILE TRANSMITTER 有权
标题翻译：多标准移动发射机功率控制系统与方法
公开(公告)号：US20120170624A1
公开(公告)日：2012-07-05
申请号：US13310434
申请日：2011-12-02
申请人： Dmitriy Rozenblit , Masoud Kahrizi , Jaleh Komaili , Rajasekhar Pullela , Shahrzad Tadjpour
发明人： Dmitriy Rozenblit , Masoud Kahrizi , Jaleh Komaili , Rajasekhar Pullela , Shahrzad Tadjpour
IPC分类号： H04W52/20 , H04B1/40 , H04L25/49
CPC分类号： H04L1/0033 , H03F1/0211 , H03F3/19 , H03F3/195 , H03F3/21 , H03F3/245 , H03F2200/451 , H03F2200/465 , H03G3/3042
摘要： A transmitter adjusts a transmitted power level by modifying a control input of a variable gain amplifier. A power amplifier control system includes an envelope extractor, an error extractor, and a feed-forward multiplier. The envelope extractor receives data signal inputs and computes the envelope of the combined signal. The error extractor generates an error signal as a function of the combined signal and the output power generated by the power amplifier. The feed-forward multiplier generates a modified error signal that is responsive to a function of the gain in a feedback path. A corresponding method for controlling a power level is also disclosed. In some embodiments, a transmit chain with a power control loop is used to adjust the transmit signal power applied at an input of a variable gain amplifier. A corresponding method for adjusting the transmit signal power level is also included.
摘要翻译：发射机通过修改可变增益放大器的控制输入来调整发射功率电平。功率放大器控制系统包括信封提取器，误差提取器和前馈乘法器。信封提取器接收数据信号输入并计算组合信号的包络。误差提取器产生作为组合信号和功率放大器产生的输出功率的函数的误差信号。前馈乘法器产生响应于反馈路径中的增益的函数的修改的误差信号。还公开了一种用于控制功率电平的相应方法。在一些实施例中，具有功率控制环路的发射链用于调整在可变增益放大器的输入处施加的发射信号功率。还包括用于调整发射信号功率电平的相应方法。

3. 发明申请

US20070072556A1 Variable gain frequency multiplier 失效
标题翻译：可变增益倍频器
公开(公告)号：US20070072556A1
公开(公告)日：2007-03-29
申请号：US11348001
申请日：2006-02-06
申请人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
发明人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A variable gain frequency multiplier comprises a multiplier circuit and a control circuit configured to receive a power control signal, the power control signal being proportional to a power output signal.
摘要翻译：可变增益倍频器包括乘法器电路和被配置为接收功率控制信号的控制电路，功率控制信号与功率输出信号成比例。

4. 发明授权

US07515880B2 Variable gain frequency multiplier 失效
标题翻译：可变增益倍频器
公开(公告)号：US07515880B2
公开(公告)日：2009-04-07
申请号：US11348001
申请日：2006-02-06
申请人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
发明人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A variable gain frequency multiplier comprises a multiplier circuit and a control circuit configured to receive a power control signal, the power control signal being proportional to a power output signal.
摘要翻译：可变增益倍频器包括乘法器电路和被配置为接收功率控制信号的控制电路，功率控制信号与功率输出信号成比例。

5. 发明申请

US20090219100A1 VOLTAGE-CONTROLLED OSCILLATOR GAIN CALIBRATION FOR TWO-POINT MODULATION IN A PHASE-LOCKED LOOP 有权
标题翻译：电压控制振荡器在相位锁定环中进行两点调制的增益校准
公开(公告)号：US20090219100A1
公开(公告)日：2009-09-03
申请号：US12040875
申请日：2008-03-01
申请人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
发明人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
IPC分类号： G01R23/00
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991
摘要： A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.
摘要翻译：锁相环（PLL）被布置成在第一输入处接收高通数据并在第二输入端接收低通数据。第一数字输入通过数模转换器（DAC）耦合到主路径，并且第二数字输入耦合到PLL的反馈路径。控制器在校准过程中提供第一个输入和第二个输入。控制器调整第一和第二控制输入，试图将输入电压保持为PLL中的压控振荡器（VCO），同时以Hz / LSB确定VCO的增益。

6. 发明授权

US07612617B2 Voltage-controlled oscillator gain calibration for two-point modulation in a phase-locked loop 有权
标题翻译：在锁相环中进行两点调制的压控振荡器增益校准
公开(公告)号：US07612617B2
公开(公告)日：2009-11-03
申请号：US12040875
申请日：2008-03-01
申请人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
发明人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
IPC分类号： H03L7/099 , H03L7/18
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991
摘要： A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.
摘要翻译：锁相环（PLL）被布置成在第一输入处接收高通数据并在第二输入端接收低通数据。第一数字输入通过数模转换器（DAC）耦合到主路径，并且第二数字输入耦合到PLL的反馈路径。控制器在校准过程中提供第一个输入和第二个输入。控制器调整第一和第二控制输入，试图将输入电压保持为PLL中的压控振荡器（VCO），同时以Hz / LSB确定VCO的增益。

7. 发明授权

US08165538B2 Systems and methods for implementing a harmonic rejection mixer 有权
标题翻译：用于实现谐波抑制混频器的系统和方法
公开(公告)号：US08165538B2
公开(公告)日：2012-04-24
申请号：US12145599
申请日：2008-06-25
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： H04B1/04 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

8. 发明授权

US07483678B2 Single chip GSM/EDGE transceiver architecture with closed loop power control 失效
标题翻译：单芯片GSM / EDGE收发器架构，具有闭环功率控制
公开(公告)号：US07483678B2
公开(公告)日：2009-01-27
申请号：US11235907
申请日：2005-09-27
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.
摘要翻译：单芯片GSM / EDGE收发器包括全差分接收链，接收链中的次谐波混频器，次谐波混频器被配置为接收射频（RF）输入信号和本地振荡器（LO）信号，该信号被相移一个标称45度的合成器，以及具有压控振荡器并具有至少一个分频器以产生所需发射和接收LO信号的合成器。收发器还包括具有闭合功率控制回路和谐波抑制调制器的发射机，其使用通过设计成允许合成器在没有倍频器的情况下开发发射和接收LO信号的频率计划成为可能。

9. 发明申请

US20070072577A1 Single chip GSM/EDGE transceiver architecture with closed loop power control 失效
标题翻译：单芯片GSM / EDGE收发器架构，具有闭环功率控制
公开(公告)号：US20070072577A1
公开(公告)日：2007-03-29
申请号：US11235907
申请日：2005-09-27
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
IPC分类号： H04B1/28 , H04M1/00 , H04B1/44
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.
摘要翻译：单芯片GSM / EDGE收发器包括全差分接收链，接收链中的次谐波混频器，次谐波混频器被配置为接收射频（RF）输入信号和本地振荡器（LO）信号，该信号被相移一个标称45度的合成器，以及具有压控振荡器并具有至少一个分频器以产生所需发射和接收LO信号的合成器。收发器还包括具有闭合功率控制回路和谐波抑制调制器的发射机，其使用通过设计成允许合成器在没有倍频器的情况下开发发射和接收LO信号的频率计划成为可能。

10. 发明授权

US08406707B2 Systems and methods for implementing a harmonic rejection mixer 有权
标题翻译：用于实现谐波抑制混频器的系统和方法
公开(公告)号：US08406707B2
公开(公告)日：2013-03-26
申请号：US13419741
申请日：2012-03-14
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： H04B1/04 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式