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    • 1. 发明授权
    • Multi-protocol configurable transceiver including configurable deskew in an integrated circuit
    • 多协议可配置收发器,包括集成电路中的可配置的偏移校正
    • US09531646B1
    • 2016-12-27
    • US12632744
    • 2009-12-07
    • Divya VijayaraghavanCurt WortmanChong H. LeeVinson Chan
    • Divya VijayaraghavanCurt WortmanChong H. LeeVinson Chan
    • G06F3/00H04L12/861G06F5/10
    • H04L49/90G06F5/10
    • Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.
    • 实施例包括可配置的多协议收发器,包括可配置的偏移电路。 在一个实施例中,可配置电路适于控制多个缓冲器的允许数据深度。 在另一个实施例中,可配置电路适于控制偏斜字符传输插入频率。 在另一个实施例中,可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。 在另一个实施例中,可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑,并且在IC的核心中布线资源,其中实现收发器用于控制至少某些去歪斜操作。 在另一个实施例中,可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理,这取决于要配置收发器的通信协议。
    • 2. 发明授权
    • Method and system for operating a communication circuit during a low-power state
    • 在低功率状态下操作通信电路的方法和系统
    • US09049120B1
    • 2015-06-02
    • US13175740
    • 2011-07-01
    • Divya VijayaraghavanChong H. Lee
    • Divya VijayaraghavanChong H. Lee
    • H04L27/00H04L12/24
    • H04L41/0833H04L12/40013Y02B60/35
    • A method and system for operating a communication circuit during periods of reduced energy consumption are disclosed. Data may be transmitted over a communication link from a first device to a second device in a low-power state. The data may be used by the second device to update coefficients and/or synchronize the receiver of the second device to a transmitter of the first device, thereby enabling a more efficient or rapid transition from the low-power state to an active state. A transmitter of the first device and a receiver of the second device may be activated before transmission of the data and deactivated after transmission of the data. In this manner, a receiver of the second device may be refreshed to enable a more efficient transition from the low-power state to an active state.
    • 公开了一种在降低能量消耗期间操作通信电路的方法和系统。 数据可以通过通信链路从低功率状态从第一设备传输到第二设备。 该数据可以被第二设备用来更新系统和/或将第二设备的接收机同步到第一设备的发射机,从而能够从低功率状态到活动状态的更有效或快速的转变。 第一设备的发射机和第二设备的接收机可以在传输数据之前激活,并且在传输数据之后停用。 以这种方式,可以刷新第二设备的接收机,以便能够从低功率状态到活动状态的更有效的转变。
    • 4. 发明授权
    • Multi-protocol channel-aggregated configurable transceiver in an integrated circuit
    • 集成电路中的多协议通道聚合可配置收发器
    • US08165191B2
    • 2012-04-24
    • US12288178
    • 2008-10-17
    • Divya VijayaraghavanCurt WortmanChong H. Lee
    • Divya VijayaraghavanCurt WortmanChong H. Lee
    • H04B1/38H04L5/16
    • H04B1/005G06F13/385H04L69/12H04L69/18
    • Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
    • 本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。 可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。 所公开的另一更具体的实施例包括通过链路范围物理编码子层(“PCS”)电路的可配置数据路径,包括链路范围时钟补偿,编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路,包括时钟补偿,编码/解码,接收块同步和物理介质访问子层(“PMA”)电路,并且还包括耦合到物理介质的位复用/解复用电路 从属(“PMD”)子层电路。
    • 7. 发明授权
    • Method and system for transitioning a communication circuit to a low-power state
    • 将通信电路转换为低功率状态的方法和系统
    • US08989284B1
    • 2015-03-24
    • US13175749
    • 2011-07-01
    • Divya VijayaraghavanChong H. Lee
    • Divya VijayaraghavanChong H. Lee
    • H04L27/00
    • H04W52/0229H04W52/0235H04W52/028Y02D70/00
    • A method and system for transitioning a communication circuit to a low-power state are disclosed. Where a first device and a second device communicate over a communication link, the first device may initiate a transition from an active state to a low-power state to conserve energy. A symbol may be encoded by the first device in data and transmitted to the second device. The first device may deactivate one or more components when entering the low-power state. Additionally, responsive to receiving and decoding the symbol, the second device may deactivate one or more components when entering the low-power state. In this manner, energy consumption of one or more components can be reduced and a low-power state may be entered to conserve energy.
    • 公开了一种将通信电路转换为低功率状态的方法和系统。 在第一设备和第二设备通过通信链路进行通信的情况下,第一设备可以发起从活动状态到低功率状态的转换以节省能量。 符号可以由数据中的第一设备编码并被发送到第二设备。 当进入低功率状态时,第一设备可以去激活一个或多个组件。 另外,响应于符号的接收和解码,第二设备可以在进入低功率状态时停用一个或多个组件。 以这种方式,可以减少一个或多个部件的能量消耗,并且可以输入低功率状态以节省能量。
    • 8. 发明授权
    • Apparatus and methods of dynamic transmit equalization
    • 动态传输均衡的装置和方法
    • US08630198B1
    • 2014-01-14
    • US12983180
    • 2010-12-31
    • Divya VijayaraghavanGopi KrishnamurthyNing XueChong H. Lee
    • Divya VijayaraghavanGopi KrishnamurthyNing XueChong H. Lee
    • G01R31/08
    • H04L25/03885H04B3/04H04B3/32H04L25/03343
    • One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry. Other embodiments, aspects, and features are also disclosed.
    • 一个实施例涉及被配置为执行双向通道的动态发送均衡的集成电路。 该集成电路包括物理编码和媒体访问控制电路之间的接口,以及在物理编码电路外部的配置成使用所述接口执行动态发送均衡的均衡控制电路。 另一个实施例涉及一种包括物理编码电路和媒体访问控制电路的收发器电路。 收发器电路还包括物理编码电路和媒体访问控制电路之间的接口以及在物理编码电路之外的均衡控制器,并且被配置为使用所述接口执行动态发送均衡。 接口被配置为以时间复用的信号格式提供从媒体访问控制电路到物理编码电路的传输系数数据。 还公开了其它实施例,方面和特征。
    • 9. 发明授权
    • Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device
    • 用于设备的多协议多数据速率自动速度协商架构
    • US08477831B2
    • 2013-07-02
    • US12860482
    • 2010-08-20
    • Divya VijayaraghavanChong H. Lee
    • Divya VijayaraghavanChong H. Lee
    • H04L27/06
    • H04L5/1446H04L1/0002H04L1/0025
    • An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.
    • 用于本地设备的接口包括可编程地配置为至少三个数据速率的发射机部分,可编程地配置为至少三个数据速率的接收机部分,以及可操作地连接到发射机部分和接收机部分的自动速度协商模块 配置发射机部分和接收机部分,以与作为这些至少三个数据速率中最好的可用数据速率的单个数据速率与远程设备进行通信。 可以通过调整发射机数据路径宽度和接收机数据路径宽度,调整所述发射机数据路径和所述接收机数据路径的频率以及过采样来调整日期速率。 可以使能或禁用字节序列化或反序列化,以根据数据速率改变数据的宽度,以传输到/从本地设备的其余部分。
    • 10. 发明申请
    • Multi-protocol channel-aggregated configurable transceiver in an integrated circuit
    • 集成电路中的多协议通道聚合可配置收发器
    • US20100215086A1
    • 2010-08-26
    • US12288178
    • 2008-10-17
    • Divya VijayaraghavanCurt WortmanChong H. Lee
    • Divya VijayaraghavanCurt WortmanChong H. Lee
    • H04B1/38
    • H04B1/005G06F13/385H04L69/12H04L69/18
    • Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
    • 本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。 可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。 所公开的另一更具体的实施例包括通过链路范围物理编码子层(“PCS”)电路的可配置数据路径,包括链路范围时钟补偿,编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路,包括时钟补偿,编码/解码,接收块同步和物理介质访问子层(“PMA”)电路,并且还包括耦合到物理介质的位复用/解复用电路 从属(“PMD”)子层电路。