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1. 发明授权

US08406073B1 Hierarchical DRAM sensing 有权
标题翻译：分层DRAM感知
公开(公告)号：US08406073B1
公开(公告)日：2013-03-26
申请号：US12928948
申请日：2010-12-22
申请人： Dinesh Somasekhar , Gunjan Pandya , Kevin Zhang , Fatih Hamzaoglu , Balaji Srinivasan , Swaroop Ghosh , Meterelliyoz Mesut
发明人： Dinesh Somasekhar , Gunjan Pandya , Kevin Zhang , Fatih Hamzaoglu , Balaji Srinivasan , Swaroop Ghosh , Meterelliyoz Mesut
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C7/065 , G11C7/08 , G11C11/4091 , G11C11/4094
摘要： A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.
摘要翻译：采用本地位线对和全局位线的分级DRAM感测装置和方法。字线选择感测放大器群集中的单元，每个放大器与一对位线相关联。选择本地位线之一用于耦合到全局位线和全局读出放大器。集群位于形成一个存储体的多个子阵列中，其中全局位线从每个存储体延伸到全局读出放大器。

2. 发明授权

US08456946B2 NAND logic word line selection 有权
标题翻译： NAND逻辑字线选择
公开(公告)号：US08456946B2
公开(公告)日：2013-06-04
申请号：US12928949
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/00
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C11/4087
摘要： A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NAND架构。低，中，高范围的分离地址用于选择最终的字线驱动。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

3. 发明授权

US08547777B2 Nor logic word line selection 有权
标题翻译：也不是逻辑字线选择
公开(公告)号：US08547777B2
公开(公告)日：2013-10-01
申请号：US12928989
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/08 , G11C8/10 , G11C8/02
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C16/08
摘要： A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NOR架构。用于选择最终字线驱动程序的低，中，高范围内单独解码的地址的完成。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

4. 发明申请

US20120163114A1 NAND logic word line selection 有权
标题翻译： NAND逻辑字线选择
公开(公告)号：US20120163114A1
公开(公告)日：2012-06-28
申请号：US12928949
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/08
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C11/4087
摘要： A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NAND架构。低，中，高范围的分离地址用于选择最终的字线驱动。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正。

5. 发明申请

US20120163115A1 Nor logic word line selection 有权
标题翻译：也不是逻辑字线选择
公开(公告)号：US20120163115A1
公开(公告)日：2012-06-28
申请号：US12928989
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/08
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C16/08
摘要： A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NOR架构。用于选择最终字线驱动程序的低，中，高范围内单独解码的地址的完成。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

6. 发明申请

US20060268626A1 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US20060268626A1
公开(公告)日：2006-11-30
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
IPC分类号： G11C7/10
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

7. 发明授权

US07403426B2 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US07403426B2
公开(公告)日：2008-07-22
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
IPC分类号： G11C11/34
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

8. 发明授权

US06879531B2 Reduced read delay for single-ended sensing 失效
标题翻译：降低单端感测的读延迟
公开(公告)号：US06879531B2
公开(公告)日：2005-04-12
申请号：US10324177
申请日：2002-12-19
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C7/12 , G11C7/22 , G11C8/08 , G11C7/00 , G11C11/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/22 , G11C8/08 , G11C2207/2281
摘要： An offset line to substantially cancel the capacitive coupling effects of a select line to a memory cell. When the select line transitions to cause a stored memory state in the memory cell to be placed onto a sense line, capacitive coupling from the select line to the sense line is substantially cancelled by capacitive coupling, of an opposite polarity, from an offset line to the sense line. Without the opposing effects of the offset line, the capacitive coupling from the select line would raise the pre-charge voltage level on the sense line, which would then require a longer time to discharge down to the input threshold of a sense gate that detects the stored state that was in the memory cell.
摘要翻译：偏移线，用于基本上消除选择线对存储器单元的电容耦合效应。当选择线转变以使得存储器单元中存储的存储器状态被放置在感测线上时，从选择线到感测线的电容耦合基本上被相反极性的电容耦合从偏移线到感觉线。没有偏移线的相反的影响，来自选择线的电容耦合将提高感测线上的预充电电压电平，这将需要更长的时间来放电到感测门的输入阈值，该感测门检测存储在存储单元中的状态。

9. 发明授权

US06351156B1 Noise reduction circuit 有权
标题翻译：降噪电路
公开(公告)号：US06351156B1
公开(公告)日：2002-02-26
申请号：US09740104
申请日：2000-12-18
申请人： Fatih Hamzaoglu , Yibin Ye , Dinesh Somasekhar , Vivek K. De
发明人： Fatih Hamzaoglu , Yibin Ye , Dinesh Somasekhar , Vivek K. De
IPC分类号： H03F345
CPC分类号： G11C7/02 , G11C7/1048 , G11C7/1051 , G11C7/1057 , G11C7/1069
摘要： A circuit and method for reducing noise in a memory circuit is disclosed. In one embodiment, the circuit includes an amplifier, a first transistor and a second transistor. The first transistor is capable of pulling up a first input port of the amplifier in response to a complement of the second memory signal. The second transistor is capable of pulling of a second input port of the amplifier in response to a complement of the first memory signal. In one embodiment, the method includes receiving a first memory signal at a first input port of an amplifier, receiving a second memory signal at a second input port of the amplifier, and pulling up the second input port in response to a complement of the first memory signal.
摘要翻译：公开了一种用于降低存储器电路中的噪声的电路和方法。在一个实施例中，电路包括放大器，第一晶体管和第二晶体管。第一晶体管能够响应于第二存储器信号的补码而提升放大器的第一输入端口。第二晶体管能够响应于第一存储器信号的补码而拉动放大器的第二输入端口。在一个实施例中，该方法包括在放大器的第一输入端口处接收第一存储器信号，在放大器的第二输入端口接收第二存储器信号，以及响应于第一输入端口记忆信号

10. 发明申请

US20060114711A1 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US20060114711A1
公开(公告)日：2006-06-01
申请号：US11001870
申请日：2004-12-01
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan Pandya , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan Pandya , Vivek De
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
摘要翻译：在一个实施例中，提供了包括一个或多个列的存储器阵列，每个列包括被分成位单元组的多个位单元，每组比特单元可控制地耦合到单独的位线。

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