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1. 发明授权

US06551927B1 CoSix process to improve junction leakage 有权
标题翻译： CoSix工艺改善结漏
公开(公告)号：US06551927B1
公开(公告)日：2003-04-22
申请号：US09880920
申请日：2001-06-15
申请人： Dian-Hau Chen , Kwang-Ming Lin , Yu-Ku Lin , Tong-Hua Kuan , Jin-Kuen Lan
发明人： Dian-Hau Chen , Kwang-Ming Lin , Yu-Ku Lin , Tong-Hua Kuan , Jin-Kuen Lan
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A cobalt silicide process having a titanium-rich/titanium nitride capping layer to improve junction leakage is described. Semiconductor device structures to be silicided are formed in and on a semiconductor substrate. A cobalt layer is deposited overlying the semiconductor device structures. A titanium-rich/titanium nitride capping layer is deposited overlying the cobalt layer. Thereafter, a cobalt silicide layer is formed on the semiconductor device structures. The titanium-rich/titanium nitride capping layer and an unreacted portion of the cobalt layer are removed to complete fabrication of the integrated circuit device.
摘要翻译：描述了具有富钛/氮化钛覆盖层以改善结漏电的硅化钴工艺。半导体衬底上形成硅化硅半导体器件结构。覆盖在半导体器件结构上的钴层被沉积。覆盖在钴层上的富钛/氮化钛覆盖层被沉积。此后，在半导体器件结构上形成钴硅化物层。除去富钛/氮化钛覆盖层和钴层的未反应部分以完成集成电路器件的制造。

2. 发明授权

US06667230B2 Passivation and planarization process for flip chip packages 有权
标题翻译：倒装芯片封装的钝化和平坦化处理
公开(公告)号：US06667230B2
公开(公告)日：2003-12-23
申请号：US09904363
申请日：2001-07-12
申请人： Dian-Hau Chen , Lin-June Wu , Kwang-Ming Lin
发明人： Dian-Hau Chen , Lin-June Wu , Kwang-Ming Lin
IPC分类号： H01L2144
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/05624 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2224/13099 , H01L2224/05552
摘要： A method including the step of forming contact pads on a semiconductor wafer. A passivation blanket is deposited over the semiconductor wafer and the contact pads. The passivation blanket includes three layers. A first layer of silicon dioxide is deposited over the semiconductor wafer and the contact pads. A second layer of silicon nitride is deposited over the first layer, and a third layer and final layer of silicon dioxide is deposited over the second layer. The passivated semiconductor wafer is planarized using an oxide chemical mechanical planarization method. Holes are opened in the passivation blanket down to the contact pads. An under bump metallurgy is deposited onto the contact pads and a portion of the final silicon dioxide layer. Solder is deposited onto the under bump metallurgy and reflown to form a flip chip having solder bumps.
摘要翻译：一种包括在半导体晶片上形成接触焊盘的步骤的方法。钝化覆盖层沉积在半导体晶片和接触焊盘上。钝化毯包括三层。在半导体晶片和接触垫上沉积第一层二氧化硅。在第一层上沉积第二层氮化硅，并在第二层上沉积第三层和最后一层二氧化硅。钝化的半导体晶片使用氧化物化学机械平面化方法进行平面化。孔在钝化毯中打开到接触垫。在接触焊盘和最后的二氧化硅层的一部分上沉积凸块下的金属。将焊料沉积在凸块下方的金属上并进行重熔以形成具有焊料凸块的倒装芯片。

3. 发明授权

US08921202B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08921202B2
公开(公告)日：2014-12-30
申请号：US12986225
申请日：2011-01-07
申请人： Geeng-Lih Lin , Kwang-Ming Lin , Shang-Hui Tu , Jui-Chun Chang
发明人： Geeng-Lih Lin , Kwang-Ming Lin , Shang-Hui Tu , Jui-Chun Chang
IPC分类号： H01L21/76 , H01L21/74 , H01L21/8249 , H01L27/06
CPC分类号： H01L29/417 , H01L21/743 , H01L21/8249 , H01L27/0623 , H01L29/0684
摘要： The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.
摘要翻译：本发明提供一种半导体器件。在衬底中形成掩埋层。在衬底中形成第一深沟槽接触结构。第一深沟槽接触结构包括导体和形成在导体的侧壁上的衬里层。第一深沟槽接触结构的底表面与埋层接触。

4. 发明授权

US5252515A Method for field inversion free multiple layer metallurgy VLSI processing 失效
标题翻译：无反向多层冶金超大规模集成电路处理方法
公开(公告)号：US5252515A
公开(公告)日：1993-10-12
申请号：US743779
申请日：1991-08-12
申请人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
发明人： Lih-Shyng Tsai , Jiunn-Jyi Lin , Kwang-Ming Lin , Shu-Lan Ying
IPC分类号： H01L21/285 , H01L21/768 , H01L21/441 , H01L21/469
CPC分类号： H01L21/76834 , H01L21/28512 , H01L21/76819 , H01L21/76828 , H01L21/76832 , H01L2924/0002 , Y10S438/958
摘要： A multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.
摘要翻译：一种多层冶金，旋涂玻璃多层冶金结构和方法，用于在具有其中的器件区域图案的半导体衬底上具有基本自由场反转的1微米或更小的特征尺寸集成电路的这种结构。钝化层位于图案的表面上方。通过钝化层将至少一些包含源极/漏极区域的器件区域的开口图案制成。图案化的第一冶金层与开口图案接触。第一通孔介电层位于第一冶金层的图案之上。富硅屏障介电层位于第一层之上。固化的旋涂玻璃层在阻挡层上。氧化硅第二通孔电介质层在旋涂玻璃层上方。开口的图案在第二通孔层，旋涂玻璃层，阻挡层和第一通孔层中。图案化的第二冶金层与开口图案接触以与第一冶金层电接触，其中完成了具有基本自由场反转的多级冶金集成电路。

5. 发明授权

US06316368B1 Method of fabricating a node contact 失效
标题翻译：制造节点接触的方法
公开(公告)号：US06316368B1
公开(公告)日：2001-11-13
申请号：US09286080
申请日：1999-04-05
申请人： Kwang-Ming Lin , Tzu-Min Peng , Chieh-Te Chen , Pang-Miao Liu
发明人： Kwang-Ming Lin , Tzu-Min Peng , Chieh-Te Chen , Pang-Miao Liu
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/76804 , H01L21/76838
摘要： A method of fabricating a node contact opening is described. A dielectric layer is formed on a substrate. A first conductive layer is formed on the dielectric layer. The first conductive layer is etched to form a trapezoidally cross-sectioned opening exposing a portion of the dielectric layer. The dielectric layer exposed by the trapezoidally cross-sectioned opening is etched to form a node contact opening in the dielectric layer exposing a part the substrate. A second conductive layer is formed to fill the node contact opening and in contact with the conductive layer.
摘要翻译：描述了制造节点接触开口的方法。在基板上形成电介质层。在介电层上形成第一导电层。蚀刻第一导电层以形成暴露电介质层的一部分的梯形截面的开口。蚀刻由梯形截面的开口暴露的电介质层，以在电介质层中形成露出衬底部分的节点接触开口。形成第二导电层以填充节点接触开口并与导电层接触。

6. 发明授权

US5334554A Nitrogen plasma treatment to prevent field device leakage in VLSI processing 失效
标题翻译：氮等离子体处理，以防止VLSI处理中的现场设备泄漏
公开(公告)号：US5334554A
公开(公告)日：1994-08-02
申请号：US825371
申请日：1992-01-24
申请人： Kwang-Ming Lin , Lih-Shyig Tsai , Jiunn-Jyi Lin , Yung-Haw Liaw
发明人： Kwang-Ming Lin , Lih-Shyig Tsai , Jiunn-Jyi Lin , Yung-Haw Liaw
IPC分类号： H01L21/768 , H01L21/469
CPC分类号： H01L21/76801 , H01L21/76819 , H01L21/76826 , H01L21/76828
摘要： A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within semiconductor substrate electrically separating certain of these source/drain regions from one another are provided. A passivation layer is formed over the surfaces of said patterns. Then the multilayer metallurgy is formed thereover by opening a pattern of openings through the passivation layer to at least some of the source/drain regions, depositing and patterning a first metallurgy layer in contact with the pattern of openings, forming a first via dielectric layer over the pattern of first metallurgy layer, exposing the first silicon oxide via dielectric layer to a nitrogen plasma, forming a spin-on-glass layer over the via dielectric layer and curing the layer, forming a second via dielectric layer over the spin-on-glass layer, forming a pattern of openings in the second via layer, the spin-on-glass layer, and the first via layer, and depositing and patterning a second metallurgy layer through the openings to make electrical contact with the first metallurgy layer.
摘要翻译：描述了一种用于形成具有基本自由场反转的一微米或更小特征尺寸集成电路的多层冶金，旋涂玻璃多层冶金的方法，即第一通孔层和SOG之间的正电荷。一种具有场效应器件源极/漏极区域的图案的半导体衬底，其栅极电介质和栅极电极结构的图案与其相关联，并且至少部分地在半导体衬底内的场隔离结构的图案将这些源极/漏极区域中的某些从提供了另一个。在所述图案的表面上形成钝化层。然后通过将通过钝化层的开口图案打开到至少一些源极/漏极区域，沉积和图案化与开口图案接触的第一冶金层，从而形成多层冶金，形成第一通孔电介质层所述第一冶金层的图案，通过介电层将所述第一氧化硅暴露于氮等离子体，在所述通孔电介质层上形成旋涂玻璃层并固化所述层，在所述自旋 - 玻璃层，在第二通孔层，旋涂玻璃层和第一通孔层中形成开口图案，并且通过开口沉积和图案化第二冶金层以与第一冶金层电接触。

7. 发明申请

US20120175727A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120175727A1
公开(公告)日：2012-07-12
申请号：US12986225
申请日：2011-01-07
申请人： Geeng-Lih Lin , Kwang-Ming Lin , Shang-Hui Tu , Jui-Chun Chang
发明人： Geeng-Lih Lin , Kwang-Ming Lin , Shang-Hui Tu , Jui-Chun Chang
IPC分类号： H01L23/48 , H01L21/283
CPC分类号： H01L29/417 , H01L21/743 , H01L21/8249 , H01L27/0623 , H01L29/0684
摘要： The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.
摘要翻译：本发明提供一种半导体器件。在衬底中形成掩埋层。在衬底中形成第一深沟槽接触结构。第一深沟槽接触结构包括导体和形成在导体的侧壁上的衬里层。第一深沟槽接触结构的底表面与埋层接触。

8. 发明申请

US20100270615A1 METHOD FOR INCREASING BREAKING DOWN VOLTAGE OF LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：增加侧向扩散金属氧化物半导体晶体管断开电压的方法
公开(公告)号：US20100270615A1
公开(公告)日：2010-10-28
申请号：US12431571
申请日：2009-04-28
申请人： Kwang-Ming Lin , Shih-Chieh Pu , Shih-Chan Chen
发明人： Kwang-Ming Lin , Shih-Chieh Pu , Shih-Chan Chen
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L29/7835 , H01L21/76224 , H01L29/0692 , H01L29/0847 , H01L29/0878 , H01L29/42368
摘要： A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region.
摘要翻译：公开了横向扩散的金属氧化物半导体晶体管。 p型块体设置在基板上。 n型阱区设置在p型体中。在p型体和n型阱区上设置多个场氧化物层。栅极结构设置在p型体的一部分和多个场氧化物层中的一个上。至少一个深沟槽隔离结构设置在p型体中并与n型阱区相邻。

9. 发明授权

US06664177B1 Dielectric ARC scheme to improve photo window in dual damascene process 有权
标题翻译：介电ARC方案改善双镶嵌工艺中的照片窗口
公开(公告)号：US06664177B1
公开(公告)日：2003-12-16
申请号：US10062645
申请日：2002-02-01
申请人： Kwang-Ming Lin , Chung-Hung Lu , Szu-An Wu , Ya-Li Tai , Kun-Yi Liu
发明人： Kwang-Ming Lin , Chung-Hung Lu , Szu-An Wu , Ya-Li Tai , Kun-Yi Liu
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76807
摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflective coating, DARC, comprised of multiple layers of silicon oxynitride, SiON, with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption. By varying both the thickness and the dielectric constant of the layers, the optical properties of light absorption, refractive indices, and light reflection are optimized.
摘要翻译：本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及通过使用由多层硅构成的介电抗反射涂层DARC来改进多层双镶嵌工艺的光刻处理窗口氧氮化物，SiON，具有不同的k，介电常数值和厚度，以减少反射率并改善光吸收。通过改变层的厚度和介电常数，优化光吸收，折射率和光反射的光学性质。

10. 发明授权

US06635576B1 Method of fabricating borderless contact using graded-stair etch stop layers 有权
标题翻译：使用梯级蚀刻停止层制造无边界接触的方法
公开(公告)号：US06635576B1
公开(公告)日：2003-10-21
申请号：US09999343
申请日：2001-12-03
申请人： Meng-Chang Liu , Lin-June Wu , Kwang-Ming Lin
发明人： Meng-Chang Liu , Lin-June Wu , Kwang-Ming Lin
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/76804 , H01L21/76832
摘要： The invention teaches the creation of borderless contact holes by using multiple layers of overlying dielectric, having different, interdependent etch rates, that function as etch stop layers for the creation of the borderless contact holes through a layer of overlying dielectric.
摘要翻译：本发明教导了通过使用具有不同的相互依赖的蚀刻速率的多层上覆电介质来形成无边界接触孔，其作为用于通过覆盖电介质层产生无边界接触孔的蚀刻停止层。

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