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1. 发明专利

JP2014132636A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014132636A
公开(公告)日：2014-07-17
申请号：JP2013214758
申请日：2013-10-15
申请人： Denso Corp , 株式会社デンソー
发明人： TOSHIDA YUMA , AKAGI NOZOMI , HAYASHI KEITA
IPC分类号： H01L29/78 , H01L21/329 , H01L21/336 , H01L29/06 , H01L29/861 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To relax concentration of injection charge to inhibit breakage of an element.SOLUTION: A semiconductor device comprises a p-type deep layer 18 which has contact with a p-type high-impurity layer 10 and a p-type column 4a and which is arranged so as to overlap between an end P1 to an end of the p-type high-impurity layer 10 when viewed from above the semiconductor device. In addition, a p-type impurity concentration of the p-type deep layer 18 is made higher than that of a p-type layer 5 and lower than that of the p-type high-impurity layer 10. By providing such p-type deep layer 18, concentration of injection charge at the time of a recovery operation can be relaxed and breakage of an element can be inhibited.
摘要翻译：要解决的问题：放松注入电荷的浓度以抑制元件断裂。解决方案：半导体器件包括p型深层18，其与p型高杂质层10和p型色谱柱接触并且当从半导体器件的上方观察时，其被布置为在p型高杂质层10的端部P1到端部之间重叠。此外，p型深层18的p型杂质浓度比p型层5的p型杂质浓度高，并且比p型高杂质层10的p型杂质浓度低。通过提供这样的p型深层18，可以放松恢复操作时的注入电荷的浓度，并且可以抑制元件的断裂。

2. 发明专利

JP2009135427A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009135427A
公开(公告)日：2009-06-18
申请号：JP2008244841
申请日：2008-09-24
申请人： Denso Corp , 株式会社デンソー
发明人： AKAGI NOZOMI , YAMAGUCHI HITOSHI , FUJII TETSUO
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a plurality of dual-face electrode elements formed using a pn column region and suppresses a short-circuit due to a transient signal while it is downsized, and also to provide a method of manufacturing the semiconductor device. SOLUTION: In the semiconductor device having a plurality of element formation regions divided by isolation separation trenches on a semiconductor substrate, pairs of electrodes are arranged on the front and rear surfaces of the semiconductor substrate to be separated from each other, and a pn column region is provided on the semiconductor substrate as a region for forming dual-face electrode elements through which currents flow between the electrodes. The isolation separation trenches are formed so that each element formation region forming the dual-face electrode element includes a p-conductivity type semiconductor region and an n-conductivity type semiconductor region forming the pn column region, and the dual-face electrode elements are formed to use the p- or n-conductivity type semiconductor region as a drift region. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其包括使用pn列区域形成的多个双面电极元件，并且在小尺寸时抑制由于瞬态信号引起的短路，并且还提供制造半导体器件的方法。解决方案：在具有多个元件形成区域的半导体器件中，由半导体衬底上的隔离分隔沟槽划分的半导体器件中，在半导体衬底的前表面和后表面上设置成一对电极以彼此分离，并且 pn列区域设置在半导体衬底上，作为用于形成电极在电极之间流动的双面电极元件的区域。形成隔离分隔沟槽，使得形成双面电极元件的各元件形成区域包括形成pn列区域的p导电型半导体区域和n导电型半导体区域，形成双面电极元件以使用p型或n型导电型半导体区域作为漂移区域。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2009135423A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009135423A
公开(公告)日：2009-06-18
申请号：JP2008231833
申请日：2008-09-10
申请人： Denso Corp , 株式会社デンソー
发明人： YAMADA AKIRA , AKAGI NOZOMI
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/8234 , H01L23/48 , H01L23/52 , H01L27/06 , H01L27/088 , H01L29/417 , H01L29/732 , H01L29/739 , H01L29/786
CPC分类号： H01L2224/48 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enable leading out of drain wiring lines to outside of source wiring lines while eliminating the need for thickening an interlayer insulating film and also enable prevention of an insulating film such as a LOCOS oxide film or an interlayer insulating film from being subjected to dielectric breakdown. SOLUTION: A rear surface electrode 19 is provided on the rear surface of an n - type drift layer 4 so as to be extended from an element zone 8 to a wiring lead-out zone 9. That is, such a structure is made that a current flows between the rear surface electrode 19 and a source wiring line 18, that is, the current is passed through the front and rear surfaces of the n - type drift layer 4 to flow in a vertical direction. The rear surface electrode 19 is extended up to the wiring lead-out zone 9 to be connected with a drain wiring line 23 through an n + type contact region 21, the n - type drift layer 4 of the wiring lead-out zone 9, an n well region 20, and an n + type contact region 21. That is, since the current flows through the rear surface electrode 19, the drain wiring line 23 is located outside of the element zone 8. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了使排水布线能够引导到源极布线外部，而不需要增厚层间绝缘膜，并且还能够防止诸如LOCOS氧化膜或层间绝缘的绝缘膜电影受到电介质击穿。解决方案：背面电极19设置在n＆lt; SP＆gt; - SP＆gt;型漂移层4的后表面上，以便从元件区8延伸到布线引出区9。也就是说，这样的结构使得电流在后表面电极19和源极布线18之间流动，即电流通过n - / SP>型的前表面和后表面漂移层4沿垂直方向流动。后表面电极19延伸到布线引出区域9，以通过n + 型接触区域21与漏极布线23连接，n - 类型漂移层4，n阱区域20和n + SP型接触区域21.也就是说，由于电流流过背面电极19，漏极布线23位于元件区8的外侧。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008282999A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008282999A
公开(公告)日：2008-11-20
申请号：JP2007126044
申请日：2007-05-10
申请人： Denso Corp , 株式会社デンソー
发明人： AKAGI NOZOMI , TAKAHASHI SHIGEKI , NAKANO TAKASHI
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress generation of a through current by controlling operation of a parasitic diode.
SOLUTION: The semiconductor device comprises a DMOS element which includes an N conduction type semiconductor layer, a P conduction type base region formed on a surface layer of one side of the semiconductor layer, an N conduction type source region formed in a surface layer of the base region, a P conduction type base contact region having an impurity concentration higher than the base region formed to be adjacent to the source region, a gate electrode located on a part of at least base region in the semiconductor layer through a gate insulating film. A trench gate electrode having a depletion layer formed in the base region is formed so that switching an applied potential to a predetermined potential with respect to the potential of the source region in the base region causes a current path between a parasitic diode formed between the base region and the semiconductor layer, and a base contact as part of the high concentration region to be closed.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过控制寄生二极管的操作来抑制通过电流的产生的半导体器件。解决方案：半导体器件包括DMOS元件，其包括N导电型半导体层，形成在半导体层的一侧的表面层上的P导电型基极区域，形成在表面的N导电型源极区域基极区的层，具有比形成为与源极区相邻的基极区高的杂质浓度的P导电型基极接触区域，通过栅极位于半导体层的至少基极区域的一部分上的栅电极绝缘膜。形成有在基极区域形成的耗尽层的沟槽栅电极被形成为使得施加的电位相对于基极区域中的源极区域的电位切换到预定电位，导致形成在基极之间的寄生二极管之间的电流路径区域和半导体层，以及作为待关闭的高浓度区域的一部分的碱接触。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2014110382A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014110382A
公开(公告)日：2014-06-12
申请号：JP2012265312
申请日：2012-12-04
申请人： Denso Corp , 株式会社デンソー
发明人： AKAGI NOZOMI , TOSHIDA YUMA , YAMAGUCHI HITOSHI
IPC分类号： H01L29/78 , H01L29/06 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To inhibit the occurrence of field concentration at positions of a peripheral region corresponding to corner parts of a cell region and cause withstand voltage to be limited by depletion layers extending in PN columns while ensuring high withstand voltage.SOLUTION: A semiconductor device comprises P-type layers 7 for forming resurf layers, which is formed by ion implantation of a P-type impurity into surface layer parts of N-type column regions 4. With this composition, the P-type impurity can be prevented from being implanted into surface layer parts of P-type column regions 5 and a concentration of the surface layer parts of the P-type column regions 5 can be inhibited from getting too dense and the P-type impurity sufficient for inverting an N-type impurity included in the N-type column regions 4 can be ion implanted. Accordingly, the occurrence of field concentration at positions of a peripheral region corresponding to corner parts of a cell region can be inhibited while ensuring high withstand voltage. In addition, a pitch of the PN columns is set smaller than a pitch of the P-type layers 7. Because of this, withstand voltage is limited by depletion layers extending in the PN columns.
摘要翻译：要解决的问题：为了抑制在与电池区域的角部相对应的周边区域的位置处的场浓度的产生，并且在确保高耐压的同时，耐受电压受到在PN列中延伸的耗尽层的限制。解决方案：半导体器件包括用于形成复合层的P型层7，其通过将P型杂质离子注入N型柱区域4的表层部分而形成。通过该组成，可以防止P型杂质注入到P型列区域5的表层部分中，并且可以抑制P型列区域5的表面层部分的浓度变得太致密，并且包含足以使N型杂质反转的P型杂质在N型柱区域4中可以离子注入。因此，能够在确保高耐受电压的同时抑制与电池区域的角部相对应的周边区域的场浓度的发生。此外，PN列的间距被设定为小于P型层7的间距。因此，耐受电压受到在PN列中延伸的耗尽层的限制。

6. 发明专利

JP2010206235A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010206235A
公开(公告)日：2010-09-16
申请号：JP2010144150
申请日：2010-06-24
申请人： Denso Corp , 株式会社デンソー
发明人： YAMADA AKIRA , AKAGI NOZOMI
IPC分类号： H01L21/76 , H01L27/088 , H01L29/78
CPC分类号： H01L2224/48 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To lead out a drain wiring outside a source wiring even without thickening an interlayer insulating film, and to prevent the insulation breakdown of an insulation film such as a LOCOS oxide film and an interlayer insulating film. SOLUTION: A lead frame 50 is disposed on the rear side of a chip. The lead frame 50 and a bonding wire 53 are connected by a drain wiring, which is routed to the chip surface side and connected to a power source wiring 52 formed on the surface side. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：即使不增厚层间绝缘膜，也可以在源极布线外引出漏极布线，并且防止诸如LOCOS氧化物膜和层间绝缘膜之类的绝缘膜的绝缘击穿。
解决方案：引线框架50设置在芯片的后侧。引线框架50和接合线53通过漏极布线连接，漏极布线被引导到芯片表面侧并连接到形成在表面侧的电源布线52。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010050155A Method of manufacturing semiconductor device, and inspecting device for semiconductor used therefor 有权
标题翻译：制造半导体器件的方法和检测其使用的半导体器件
公开(公告)号：JP2010050155A
公开(公告)日：2010-03-04
申请号：JP2008210907
申请日：2008-08-19
申请人： Denso Corp , 株式会社デンソー
发明人： KITAMURA YASUHIRO , KASEDA KANAME , SUZUKI TOMOHISA , AKAGI NOZOMI
IPC分类号： H01L21/66 , G01R1/073 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, having first and second back-surface conductors 3 and 4 provided to the back surface of a semiconductor substrate 1, which includes an inspecting process of inspecting the semiconductor device without dividing the semiconductor substrate 1 into chips, and to provide an inspecting device for the semiconductor used therefor.
SOLUTION: An intermediate wiring layer 30 is prepared which is a plate-like member, and includes an insulating portion 31 constituting the plate-like member and first and second conduction portions 32 and 33 provided to be exposed from the front surface and back surface of the insulating portion 31, and in which the first conduction portion 32 and second conduction portion 33 are insulated. Then, the intermediate wiring layer 30 is disposed such that the first conduction portion 32 and first back-surface conductor 3 are electrically connected to the back surface of the semiconductor substrate 1, and the second conduction portion 33 and second back-surface conductor 4 are electrically connected, and a voltage is applied between the first and second back-surface conductors 3 and 4 through the first and second conduction portions 32 and 33.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，其具有设置在半导体衬底1的背面的第一和第二背表面导体3和4，其包括检查半导体器件的检查过程而不将半导体衬底1分成芯片，并提供用于其的半导体检测装置。
解决方案：制备中间布线层30，其为板状构件，并且包括构成板状构件的绝缘部分31和设置成从前表面露出的第一和第二导电部分32和33;以及绝缘部31的背面，第一导电部32和第二导通部33绝缘。然后，中间布线层30配置成使得第一导电部32和第一背面导体3与半导体基板1的背面电连接，第二导通部33和第二背面导体4 电连接，并且通过第一和第二导电部分32和33在第一和第二背表面导体3和4之间施加电压。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2008153403A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008153403A
公开(公告)日：2008-07-03
申请号：JP2006339219
申请日：2006-12-15
申请人： Denso Corp , 株式会社デンソー
发明人： AKAGI NOZOMI , FUJII TETSUO
IPC分类号： H01L21/76 , H01L21/762 , H01L21/822 , H01L27/04 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To provide a small semiconductor device in which malfunction because of fluctuation and noise in a power line is hard to occur and which can inexpensively be manufactured. SOLUTION: In a SOI substrate 20 having a buried oxide film 12, a SOI layer 21 on the buried oxide film 12 is divided into a plurality of regions E1, E2 and D surrounded by an insulating isolation trench reaching the buried oxide film 12. A plurality of regions E1, E2 and D are classified into element regions E1 and E2 where active elements or passive elements are arranged, and the isolation region D which surrounds the element regions E1 and E2 in a substrate face and is fixed to ground (GND) potential. A capacitance element C1 where the SOI layer 21 of the isolation region D is set to be one electrode is arranged in the isolation region D of the semiconductor device 101. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种小型半导体器件，其中由于电力线中的波动和噪声而导致的故障难以发生并且可以廉价地制造。解决方案：在具有掩埋氧化膜12的SOI衬底20中，掩埋氧化膜12上的SOI层21被分成由到达掩埋氧化膜的绝缘隔离沟道围绕的多个区域E1，E2和D 多个区域E1，E2和D分为元件区域E1和E2，其中布置有源元件或无源元件，以及隔离区域D，其围绕衬底面中的元件区域E1和E2并固定到地面（GND）电位。隔离区域D的SOI层21被设置为一个电极的电容元件C1被布置在半导体器件101的隔离区域D中。（C）2008，JPO＆INPIT

9. 发明专利

JP2008067140A Switching circuit 有权
标题翻译：切换电路
公开(公告)号：JP2008067140A
公开(公告)日：2008-03-21
申请号：JP2006243832
申请日：2006-09-08
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： HATSUTORI YOSHIKUNI , KUWABARA MAKOTO , OKADA KYOKO , MIZUNO SHOJI , AOKI TAKAAKI , TAKAHASHI SHIGEKI , AKAGI NOZOMI , NAKANO TAKASHI
IPC分类号： H03K17/16 , H03K17/687
摘要： PROBLEM TO BE SOLVED: To provide a switching circuit of a transistor in which an increase in surge voltage is suppressed.
SOLUTION: The switching circuit 10 is provided with: a transistor 50 which is used by serially connecting a power source 80 and a load 70 between a drain electrode D and a source electrode; a control circuit 40 which outputs drive voltage Vin to the transistor; and a serial circuit 30 which is connected between a gate electrode G and the drain electrode D of the transistor 50 and in which a first capacitor 32 and a first diode 34 are serially connected with each other. A cathode of the first diode 34 is connected on the side of the gate electrode G of the transistor 50 and an anode of the first diode 34 is connected on the side of the drain electrode D of the transistor 50. The switching circuit 10 is further provided with a voltage regulator circuit 20 which is connected to a connection line between the first capacitor 32 and the first diode 34 and adjusts voltage of the connection line.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供抑制浪涌电压增加的晶体管的开关电路。解决方案：开关电路10设置有：晶体管50，其通过串联连接电源80和漏电极D与源电极之间的负载70而使用; 将驱动电压Vin输出到晶体管的控制电路40; 以及串联电路30，其连接在晶体管50的栅极电极G和漏极电极D之间，并且其中第一电容器32和第一二极管34彼此串联连接。第一二极管34的阴极连接在晶体管50的栅极电极G的一侧，第一二极管34的阳极连接在晶体管50的漏电极D侧。另外，开关电路10 设置有电压调节器电路20，其连接到第一电容器32和第一二极管34之间的连接线，并且调节连接线的电压。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2013138171A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013138171A
公开(公告)日：2013-07-11
申请号：JP2012178674
申请日：2012-08-10
申请人： Denso Corp , 株式会社デンソー
发明人： TOSHIDA YUMA , AKAGI NOZOMI
IPC分类号： H01L29/78 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve withstanding voltage yield by inhibiting a peripheral region from reducing charge balance margin of a cell region.SOLUTION: A semiconductor device comprises: a cell region 1 in which N-type column regions 4 and P-type column regions 5 form a super junction structure and an N-type charge amount in the N-type column regions 4 and a P-type charge amount in the P-type column regions 5 are made equal to each other; and a peripheral region 2 including a charge balance change region 27 in which an N-type charge amount in the super junction structure is gradually made larger than the P-type charge amount with the decreasing distance from a periphery of the cell region 1.
摘要翻译：要解决的问题：提供一种半导体器件，其可以通过抑制周边区域减小电池区域的电荷平衡裕度来提高耐压产生。解决方案：半导体器件包括：单元区域1，其中N型列区域4 P型列区域5形成超结结构，N型列区域4中的N型电荷量和P型列区域5中的P型电荷量彼此相等; 以及包含电荷平衡变化区域27的外围区域2，其中超导结结构中的N型电荷量随着从单元区域1的周边的距离减小而逐渐变得大于P型电荷量。

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