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1. 发明申请

US20060149918A1 Memory with modifiable address map 审中-公开
标题翻译：内存可修改地址图
公开(公告)号：US20060149918A1
公开(公告)日：2006-07-06
申请号：US11323473
申请日：2005-12-30
申请人： John Rudelic , Dennis O'Connor , Mark Fullerton , Ray Richardson
发明人： John Rudelic , Dennis O'Connor , Mark Fullerton , Ray Richardson
IPC分类号： G06F12/10
CPC分类号： G06F12/1441 , G06F12/0246 , G06F2212/1052 , G06F2212/7201
摘要： A memory device includes a flag register to modify the address map of the memory device based on the state of an input node on the memory device.
摘要翻译：存储器件包括标志寄存器，用于根据存储器件上的输入节点的状态修改存储器件的地址映射。

2. 发明申请

US20060129710A1 Programmable transaction initiator architecture for systems with secure and non-secure modes 失效
公开(公告)号：US20060129710A1
公开(公告)日：2006-06-15
申请号：US11013217
申请日：2004-12-14
申请人： Dennis O'Connor , Mark Fullerton
发明人： Dennis O'Connor , Mark Fullerton
IPC分类号： G06F13/28
CPC分类号： G06F21/79 , G06F13/28 , G06F21/71 , G06F2221/2105
摘要： A wireless device dynamically programs a control register for a command-chain driven DMA device. The control register stores a beginning address of the linked list of commands and a secure bit. The secure bit is set if the transaction writing register is secure and a bit in the data being written into the register is set. DMA devices and other bus-mastering peripherals perform tasks described via a command chain that has access to secure resources when the processor is operating in the secure mode and the secure bit is set.

3. 发明申请

US20060143687A1 Secure controller for block oriented storage 有权
公开(公告)号：US20060143687A1
公开(公告)日：2006-06-29
申请号：US11027913
申请日：2004-12-28
申请人： Dennis O'Connor , Mark Fullerton , Ray Richardson
发明人： Dennis O'Connor , Mark Fullerton , Ray Richardson
IPC分类号： H04L9/00
CPC分类号： G06F21/74 , G06F21/79
摘要： A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

4. 发明申请

US20060149917A1 Secure memory controller 有权
标题翻译：安全的内存控制器
公开(公告)号：US20060149917A1
公开(公告)日：2006-07-06
申请号：US11027784
申请日：2004-12-30
申请人： Dennis O'Connor , Mark Fullerton , Ray Richardson
发明人： Dennis O'Connor , Mark Fullerton , Ray Richardson
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： A memory controller partitions memory into secure partitions and non-secure partitions.
摘要翻译：内存控制器将内存分为安全分区和非安全分区。

5. 发明申请

US20070192830A1 Security module having access limited based upon security level of code seeking access 审中-公开
标题翻译：基于代码寻求访问的安全级别的访问受限的安全模块
公开(公告)号：US20070192830A1
公开(公告)日：2007-08-16
申请号：US11354676
申请日：2006-02-15
申请人： Dennis O'Connor
发明人： Dennis O'Connor
IPC分类号： H04L9/32
CPC分类号： G06F21/629 , G06F21/6218 , G06F2221/2113
摘要： Access to secrets and/or security related functionality within a security module (e.g., a platform trust module, etc.) is limited based upon a security level associated with a program seeking access to the secrets/functionality within a digital platform.
摘要翻译：基于与寻求访问数字平台内的秘密/功能的程序相关联的安全级别来限制安全模块（例如，平台信任模块等）中的秘密和/或安全相关功能的访问。

6. 发明授权

US5561782A Pipelined cache system having low effective latency for nonsequential accesses 失效
标题翻译：流水线缓存系统对于非顺序访问具有低有效等待时间
公开(公告)号：US5561782A
公开(公告)日：1996-10-01
申请号：US269650
申请日：1994-06-30
申请人： Dennis O'Connor
发明人： Dennis O'Connor
IPC分类号： G06F9/38 , G06F12/08 , G06F9/32 , G06F13/00
CPC分类号： G06F12/0855 , G06F9/3808
摘要： A method and apparatus for reducing the effective latency for nonsequential memory accesses is disclosed. An improved cache includes a multi-stage pipelined cache that provides at least one cache output record in response to a record address hitting the pipelined cache. The pipelined cache provides the record after an idle period of L clock cycles in which the pipelined cache provides no output records. The effective latency of the pipelined cache is reduced by providing a branch target cache (BTC) that issues at least one record during the idle period in response to a nonsequential record address hitting the BTC. The records stored in the caches may, for example, represent instructions. The cache further includes a lookahead circuit for providing the nonsequential record address (A) and a lookahead address (A+(L.times.W), where W denotes the issue width) to the pipelined cache during a zero cycle preceding the idle period. The pipelined cache respectively provides a nonsequential record and a lookahead record from the lookahead address after the idle period in response to the nonsequential record address and the lookahead address hitting the pipelined cache. A multiplexer selects the nonsequential record from the pipelined cache as an output if the nonsequential address misses the BTC. The multiplexer selects the lookahead record as the output if the nonsequential address hits the BTC. Various modifications of this technique are also described.
摘要翻译：公开了一种减少非顺序存储器访问的有效等待时间的方法和装置。改进的高速缓存包括多级流水线缓存，其响应于触发流水线缓存的记录地址而提供至少一个高速缓存输出记录。流水线缓存在L个时钟周期的空闲周期之后提供记录，其中流水线缓存不提供输出记录。流水线缓存的有效延迟通过提供在空闲周期期间响应于不依赖的记录地址击中BTC而发出至少一个记录的分支目标高速缓存（BTC）来减少。存储在高速缓存中的记录可以例如表示指令。高速缓存还包括用于在空闲周期之前的零周期期间向流水线高速缓存提供非顺序记录地址（A）和前瞻性地址（A +（LxW），其中W表示发布宽度）的查找电路。流水线缓存分别响应于非顺序记录地址和查找流水线缓存的前瞻性地址，在空闲周期之后分别提供来自前瞻地址的非顺序记录和查找记录。如果非顺序地址错过了BTC，则多路复用器从流水线缓存中选择非顺序记录作为输出。如果非顺序地址匹配BTC，则多路复用器选择前瞻记录作为输出。还描述了该技术的各种修改。

7. 发明授权

US10231533B2 Wearable pack 有权
公开(公告)号：US10231533B2
公开(公告)日：2019-03-19
申请号：US15584067
申请日：2017-05-02
申请人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
发明人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
IPC分类号： A45F3/06 , F41H1/00 , F41H5/00 , A45F4/02 , A41D1/04 , F41H1/02
摘要： A wearable container or pack that is quickly convertible into front and rear body armor without removing the pack from the torso of the wearer. The container or pack may include a bag that may be easily separated from the container or pack, and quickly dropped from the container or pack, providing supplies for another person.

8. 发明申请

US20170318941A1 WEARABLE PACK 审中-公开
公开(公告)号：US20170318941A1
公开(公告)日：2017-11-09
申请号：US15584067
申请日：2017-05-02
申请人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
发明人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
IPC分类号： A45F3/06 , F41H1/02 , A41D1/04
CPC分类号： A45F3/06 , A41D1/04 , A45C2003/005 , A45F3/04 , A45F4/02 , A45F2003/045 , F41H1/00 , F41H1/02 , F41H5/00
摘要： A wearable container or pack that is quickly convertible into front and rear body armor without removing the pack from the torso of the wearer. The container or pack may include a bag that may be easily separated from the container or pack, and quickly dropped from the container or pack, providing supplies for another person.

9. 发明申请

US20070204121A1 Moveable locked lines in a multi-level cache 有权
标题翻译：多级缓存中的可移动锁定行
公开(公告)号：US20070204121A1
公开(公告)日：2007-08-30
申请号：US11361228
申请日：2006-02-24
申请人： Dennis O'Connor , Michael Morrow , Stephen Strazdus
发明人： Dennis O'Connor , Michael Morrow , Stephen Strazdus
IPC分类号： G06F12/14
CPC分类号： G06F12/0811 , G06F12/0871 , G06F12/0888 , G06F12/126 , G06F12/128
摘要： A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move back and forth within the cache hierarchy. The cache line may be evicted from the cache hierarchy after the lock property is removed.
摘要翻译：处理器包括多级缓存层级，其中锁属性与高速缓存线相关联。缓存行保留锁定属性，并且可以在缓存层次结构内来回移动。在锁定属性被删除后，缓存行可以从缓存层次结构中逐出。

10. 发明申请

US20070106871A1 Processor multi-partition security architecture 有权
标题翻译：处理器多分区安全架构
公开(公告)号：US20070106871A1
公开(公告)日：2007-05-10
申请号：US11271778
申请日：2005-11-10
申请人： Dennis O'Connor
发明人： Dennis O'Connor
IPC分类号： G06F12/00
CPC分类号： G06F12/1475 , G06F12/1441
摘要： A state machine may be coupled to a memory management unit configuration table (MMUCT) stored in a memory to index an entry from the MMUCT. A parameter associated with the entry may be used to control operations associated with a memory management unit (MMU). The MMU may be used to control access to a set of page tables stored in the memory. Other embodiments may be described and claimed.
摘要翻译：状态机可以耦合到存储在存储器中的存储器管理单元配置表（MMUCT），以对来自MMUCT的条目进行索引。与条目相关联的参数可以用于控制与存储器管理单元（MMU）相关联的操作。 MMU可以用于控制对存储在存储器中的一组页表的访问。可以描述和要求保护其他实施例。

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