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1. 发明授权

US10231533B2 Wearable pack 有权
公开(公告)号：US10231533B2
公开(公告)日：2019-03-19
申请号：US15584067
申请日：2017-05-02
申请人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
发明人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
IPC分类号： A45F3/06 , F41H1/00 , F41H5/00 , A45F4/02 , A41D1/04 , F41H1/02
摘要： A wearable container or pack that is quickly convertible into front and rear body armor without removing the pack from the torso of the wearer. The container or pack may include a bag that may be easily separated from the container or pack, and quickly dropped from the container or pack, providing supplies for another person.

2. 发明申请

US20170318941A1 WEARABLE PACK 审中-公开
公开(公告)号：US20170318941A1
公开(公告)日：2017-11-09
申请号：US15584067
申请日：2017-05-02
申请人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
发明人： Robert Vaughan , Dennis O'Connor , Brian Naillon , Von Bolin , Wallace Lau
IPC分类号： A45F3/06 , F41H1/02 , A41D1/04
CPC分类号： A45F3/06 , A41D1/04 , A45C2003/005 , A45F3/04 , A45F4/02 , A45F2003/045 , F41H1/00 , F41H1/02 , F41H5/00
摘要： A wearable container or pack that is quickly convertible into front and rear body armor without removing the pack from the torso of the wearer. The container or pack may include a bag that may be easily separated from the container or pack, and quickly dropped from the container or pack, providing supplies for another person.

3. 发明申请

US20070192830A1 Security module having access limited based upon security level of code seeking access 审中-公开
标题翻译：基于代码寻求访问的安全级别的访问受限的安全模块
公开(公告)号：US20070192830A1
公开(公告)日：2007-08-16
申请号：US11354676
申请日：2006-02-15
申请人： Dennis O'Connor
发明人： Dennis O'Connor
IPC分类号： H04L9/32
CPC分类号： G06F21/629 , G06F21/6218 , G06F2221/2113
摘要： Access to secrets and/or security related functionality within a security module (e.g., a platform trust module, etc.) is limited based upon a security level associated with a program seeking access to the secrets/functionality within a digital platform.
摘要翻译：基于与寻求访问数字平台内的秘密/功能的程序相关联的安全级别来限制安全模块（例如，平台信任模块等）中的秘密和/或安全相关功能的访问。

4. 发明授权

US5561782A Pipelined cache system having low effective latency for nonsequential accesses 失效
标题翻译：流水线缓存系统对于非顺序访问具有低有效等待时间
公开(公告)号：US5561782A
公开(公告)日：1996-10-01
申请号：US269650
申请日：1994-06-30
申请人： Dennis O'Connor
发明人： Dennis O'Connor
IPC分类号： G06F9/38 , G06F12/08 , G06F9/32 , G06F13/00
CPC分类号： G06F12/0855 , G06F9/3808
摘要： A method and apparatus for reducing the effective latency for nonsequential memory accesses is disclosed. An improved cache includes a multi-stage pipelined cache that provides at least one cache output record in response to a record address hitting the pipelined cache. The pipelined cache provides the record after an idle period of L clock cycles in which the pipelined cache provides no output records. The effective latency of the pipelined cache is reduced by providing a branch target cache (BTC) that issues at least one record during the idle period in response to a nonsequential record address hitting the BTC. The records stored in the caches may, for example, represent instructions. The cache further includes a lookahead circuit for providing the nonsequential record address (A) and a lookahead address (A+(L.times.W), where W denotes the issue width) to the pipelined cache during a zero cycle preceding the idle period. The pipelined cache respectively provides a nonsequential record and a lookahead record from the lookahead address after the idle period in response to the nonsequential record address and the lookahead address hitting the pipelined cache. A multiplexer selects the nonsequential record from the pipelined cache as an output if the nonsequential address misses the BTC. The multiplexer selects the lookahead record as the output if the nonsequential address hits the BTC. Various modifications of this technique are also described.
摘要翻译：公开了一种减少非顺序存储器访问的有效等待时间的方法和装置。改进的高速缓存包括多级流水线缓存，其响应于触发流水线缓存的记录地址而提供至少一个高速缓存输出记录。流水线缓存在L个时钟周期的空闲周期之后提供记录，其中流水线缓存不提供输出记录。流水线缓存的有效延迟通过提供在空闲周期期间响应于不依赖的记录地址击中BTC而发出至少一个记录的分支目标高速缓存（BTC）来减少。存储在高速缓存中的记录可以例如表示指令。高速缓存还包括用于在空闲周期之前的零周期期间向流水线高速缓存提供非顺序记录地址（A）和前瞻性地址（A +（LxW），其中W表示发布宽度）的查找电路。流水线缓存分别响应于非顺序记录地址和查找流水线缓存的前瞻性地址，在空闲周期之后分别提供来自前瞻地址的非顺序记录和查找记录。如果非顺序地址错过了BTC，则多路复用器从流水线缓存中选择非顺序记录作为输出。如果非顺序地址匹配BTC，则多路复用器选择前瞻记录作为输出。还描述了该技术的各种修改。

5. 发明申请

US20070204121A1 Moveable locked lines in a multi-level cache 有权
标题翻译：多级缓存中的可移动锁定行
公开(公告)号：US20070204121A1
公开(公告)日：2007-08-30
申请号：US11361228
申请日：2006-02-24
申请人： Dennis O'Connor , Michael Morrow , Stephen Strazdus
发明人： Dennis O'Connor , Michael Morrow , Stephen Strazdus
IPC分类号： G06F12/14
CPC分类号： G06F12/0811 , G06F12/0871 , G06F12/0888 , G06F12/126 , G06F12/128
摘要： A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move back and forth within the cache hierarchy. The cache line may be evicted from the cache hierarchy after the lock property is removed.
摘要翻译：处理器包括多级缓存层级，其中锁属性与高速缓存线相关联。缓存行保留锁定属性，并且可以在缓存层次结构内来回移动。在锁定属性被删除后，缓存行可以从缓存层次结构中逐出。

6. 发明申请

US20070106871A1 Processor multi-partition security architecture 有权
标题翻译：处理器多分区安全架构
公开(公告)号：US20070106871A1
公开(公告)日：2007-05-10
申请号：US11271778
申请日：2005-11-10
申请人： Dennis O'Connor
发明人： Dennis O'Connor
IPC分类号： G06F12/00
CPC分类号： G06F12/1475 , G06F12/1441
摘要： A state machine may be coupled to a memory management unit configuration table (MMUCT) stored in a memory to index an entry from the MMUCT. A parameter associated with the entry may be used to control operations associated with a memory management unit (MMU). The MMU may be used to control access to a set of page tables stored in the memory. Other embodiments may be described and claimed.
摘要翻译：状态机可以耦合到存储在存储器中的存储器管理单元配置表（MMUCT），以对来自MMUCT的条目进行索引。与条目相关联的参数可以用于控制与存储器管理单元（MMU）相关联的操作。 MMU可以用于控制对存储在存储器中的一组页表的访问。可以描述和要求保护其他实施例。

7. 发明申请

US20060224834A1 Write-back cache methods and apparatus 有权
标题翻译：回写缓存方法和装置
公开(公告)号：US20060224834A1
公开(公告)日：2006-10-05
申请号：US11094687
申请日：2005-03-30
申请人： Dennis O'Connor , Michael Morrow
发明人： Dennis O'Connor , Michael Morrow
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0815
摘要： A cache controller prevents the use of data in a write-back cache memory from being propagated until the data is backed-up in a main memory. Control bits inhibit portions of the cache memory from being accessed.
摘要翻译：高速缓存控制器防止在回写高速缓冲存储器中的数据的使用被传播，直到数据被备份在主存储器中。控制位禁止高速缓冲存储器的部分被访问。

8. 发明申请

US20060143687A1 Secure controller for block oriented storage 有权
公开(公告)号：US20060143687A1
公开(公告)日：2006-06-29
申请号：US11027913
申请日：2004-12-28
申请人： Dennis O'Connor , Mark Fullerton , Ray Richardson
发明人： Dennis O'Connor , Mark Fullerton , Ray Richardson
IPC分类号： H04L9/00
CPC分类号： G06F21/74 , G06F21/79
摘要： A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

9. 发明申请

US20050244138A1 Time shifting by simultaneously recording and playing a data stream 审中-公开
标题翻译：通过同时记录和播放数据流进行时移
公开(公告)号：US20050244138A1
公开(公告)日：2005-11-03
申请号：US11174906
申请日：2005-07-05
申请人： Dennis O'Connor , Mark Chuang
发明人： Dennis O'Connor , Mark Chuang
IPC分类号： G11B27/034 , G11B27/10 , H04N5/76 , H04N5/781 , H04N5/85 , H04N5/907
CPC分类号： H04N21/4147 , G11B27/034 , G11B27/105 , G11B2020/10962 , G11B2220/218 , G11B2220/2516 , G11B2220/2545 , G11B2220/2562 , G11B2220/455 , G11B2220/61 , H04N5/76 , H04N5/781 , H04N5/85 , H04N5/907
摘要： A video stream may include portions that are stored while other portions are being displayed. In one embodiment, a portion of the video stream may be stored in digital storage media at one instance while in the next instance another portion of the stream is being read out of the storage media.
摘要翻译：视频流可以包括在显示其他部分时存储的部分。在一个实施例中，视频流的一部分可以在一个实例处存储在数字存储介质中，而在下一个例子中，流的另一部分正在从存储介质读出。

10. 发明授权

US5905902A Programmable state machine employing a cache-like arrangement 失效
标题翻译：采用缓存式布置的可编程状态机
公开(公告)号：US5905902A
公开(公告)日：1999-05-18
申请号：US537155
申请日：1995-09-28
申请人： Dennis O'Connor
发明人： Dennis O'Connor
IPC分类号： G05B19/042 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0875 , G05B19/0426 , G05B2219/23289
摘要： The programmable state machine includes a tag entry array and a new state array. All permissible combinations of current states and input values are represented within the tag entry array. The corresponding new state, to be transitioned to for each combination of current states and input values, is stored in the new state array. The tag entry array receives the current state and the input signals and generates a hit signal identifying which of the tag entries corresponds to the current state and input value signals. The new state array outputs the corresponding new state, based upon the hit signal received. In one embodiment, the tag entry array is configured as a fully associative cache tag entry array. In another embodiment, the tag entry array is configured as a set associative cache array. To eliminate the need to redundantly store a single new state, that corresponds to a large number of different transitions, a compare under mask arrangement is provided. As an alternative, a default new state arrangement is provided which outputs a default new state if a miss is detected within the tag entry array.
摘要翻译：可编程状态机包括标签输入阵列和新的状态阵列。当前状态和输入值的所有允许的组合在标签条目数组中表示。要转换到当前状态和输入值的每个组合的相应的新状态存储在新的状态数组中。标签条目阵列接收当前状态和输入信号，并产生一个命中信号，该命中信号标识哪个标签条目对应于当前状态和输入值信号。新状态阵列根据接收的命中信号输出相应的新状态。在一个实施例中，标签条目阵列被配置为完全关联的高速缓存标签条目阵列。在另一个实施例中，标签条目阵列被配置为集合关联高速缓存阵列。为了消除冗余存储单个新状态的需要，其对应于大量不同的转换，提供了掩码布置下的比较。作为替代，提供了默认的新状态布置，如果在标签条目阵列内检测到未命中则输出默认的新状态。

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