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    • 5. 发明授权
    • Interface between a host and a slave device having a latency greater than the latency of the host
    • 主机和从设备之间的接口具有大于主机延迟的延迟
    • US07054971B2
    • 2006-05-30
    • US10391913
    • 2003-03-19
    • Denis BeaudoinPatrick Wai-Tong Leung
    • Denis BeaudoinPatrick Wai-Tong Leung
    • G06F12/00
    • G06F13/4027
    • An interface between a host and a slave device having a latency greater than the latency of the host is disclosed. The interface includes a register and a state machine. The state machine provides data to the host from any address in the slave in two host read cycles. The state machine receives a first request from the host for data stored at a first address in the slave at a first time. The state machine stores the data returned from the slave in response to the first request in the register at a second time. The state machine receives a second request from the host for data stored at a second address in the slave at a third time. The state machine provides the data specified in the first request to the host at a fourth time. The state machine is additionally adapted to provide data to the host from a second address in the slave in one read cycle.
    • 公开了主机与从设备之间的接口,其间延迟大于主机的等待时间。 该接口包括寄存器和状态机。 状态机在两个主机读取周期中从主机中的任何地址向主机提供数据。 状态机在第一时间从主机接收存储在从机中的第一地址处的数据的第一请求。 状态机在第二次存储从从机返回的数据以响应于第一请求在寄存器中。 状态机在第三时间从主机接收存储在从属设备的第二地址上的数据的第二请求。 状态机将第一次请求中指定的数据第四次提供给主机。 状态机还适于在一个读取周期中从从站中的第二地址向主机提供数据。
    • 9. 发明授权
    • UART emulator card
    • UART仿真器卡
    • US5604870A
    • 1997-02-18
    • US283365
    • 1994-08-01
    • Barry MossDenis Beaudoin
    • Barry MossDenis Beaudoin
    • G06F13/10G06F13/00
    • G06F13/105
    • An interface device (102) and corresponding method for coupling a peripheral controller (117) to a host computer (100), the interface device including an emulated universal asynchronous receiver transmitter (UART) (113) for the host computer. The interface device further includes a plurality of registers (203), preferably a control (215), status (227), and data register, such as a multi-register data buffer (401), corresponding to the registers of a UART, a host computer port (112), preferably compatible with a PCMCIA standard, that includes an address map for the plurality of registers (203), a peripheral controller port (114) providing an address mapped parallel interface to the plurality of registers (203), and control logic (207) for providing status signals, including UART status signals, to the host computer port and to the peripheral controller port. The interface device may further include a pacing circuit (303) for substantially emulating, preferably dependent on a baud rate of the data information, the timing limitations of the UART.
    • 一种用于将外围控制器(117)耦合到主计算机(100)的接口设备(102)和相应的方法,所述接口设备包括用于所述主计算机的仿真通用异步接收机发射机(UART)(113)。 接口设备还包括多个寄存器(203),优选地是控制(215),状态(227)以及数据寄存器,诸如多寄存器数据缓冲器(401),对应于UART的寄存器, 主机计算机端口(112),优选地与PCMCIA标准兼容,其包括用于所述多个寄存器(203)的地址映射,提供与所述多个寄存器(203)的地址映射并行接口的外围控制器端口(114) 以及用于向主计算机端口和外围控制器端口提供包括UART状态信号的状态信号的控制逻辑(207)。 接口设备还可以包括起搏电路(303),用于基本仿真,优选地依赖于数据信息的波特率,UART的定时限制。
    • 10. 发明申请
    • Very little multi master bus
    • 很少的多主车
    • US20060136635A1
    • 2006-06-22
    • US11020830
    • 2004-12-22
    • Denis BeaudoinChristopher TracyBrian Karguth
    • Denis BeaudoinChristopher TracyBrian Karguth
    • G06F13/00
    • G06F13/374
    • A method and an apparatus for communication among multiple devices on a data bus with relatively few connections to the bus and reduced logic for enumeration, arbitration, and data flow control is described. A Very Little Multi Master Bus (VLMMB) couples various devices in a bit-rotated manner. When one or more devices seek ownership (control) of the bus, that device raises its assigned bus request line to a predetermined logic (e.g., “1” or “0”). Because there are as many bus request lines as devices, each device can “see” the devices requesting the ownership of the bus. If multiple devices request ownership, the requesting devices determine which one gains ownership by a hierarchical, round-robin, or similar logical decision.
    • 描述了一种用于在数据总线上的多个设备之间进行通信的方法和装置,其中与总线的连接相对较少,并且用于枚举,仲裁和数据流控制的减少的逻辑。 非常小的多主总线(VLMMB)以位旋转的方式耦合各种设备。 当一个或多个设备寻求总线的所有权(控制)时,该设备将其分配的总线请求线提升到预定逻辑(例如,“1”或“0”)。 因为有与设备一样多的总线请求线路,每个设备都可以“查看”请求总线所有权的设备。 如果多个设备请求所有权,则请求设备确定哪个通过分级,循环或类似的逻辑决策来获得所有权。