专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09396062B1 Group based codes for multi-dimensional recording (MDR) 有权
标题翻译：用于多维记录（MDR）的基于组的代码
公开(公告)号：US09396062B1
公开(公告)日：2016-07-19
申请号：US14245886
申请日：2014-04-04
申请人： Deepak Sridhara , William Radich , Ara Patapoutian , Timothy R Feldman , Mark Gaertner
发明人： Deepak Sridhara , William Radich , Ara Patapoutian , Timothy R Feldman , Mark Gaertner
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1044 , G06F11/1008 , G06F11/1068
摘要： A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.
摘要翻译：多维记录（MDR）系统可以包括基于组的编码电路（GBCC），其可以通过外部代码实现纠错码。 GBCC可以在其中内部码字包括多个存储器分组的MDR系统中实现外部代码，包括交织外部代码。多个存储器分组可以跨数据存储介质中的不同结构划分; 或者可以跨越多个不同的数据存储介质。

2. 发明授权

US08943384B2 Using a soft decoder with hard data 有权
标题翻译：使用具有硬数据的软解码器
公开(公告)号：US08943384B2
公开(公告)日：2015-01-27
申请号：US13445591
申请日：2012-04-12
申请人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
发明人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1048 , G11C11/5642 , H03M13/1111 , H03M13/2957 , H03M13/3707 , H03M13/6325 , H03M13/6511 , H03M13/6577
摘要： A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.
摘要翻译：用于重新使用软解码器的方法包括从存储器设备中的存储器单元接收软数据和硬数据，将软数据映射到第一组软信息，将硬数据映射到第二组软信息，并使用软解码器解码第一组和第二组软信息。

3. 发明申请

US20130275829A1 USING A SOFT DECODER WITH HARD DATA 有权
标题翻译：使用硬数据的软解码器
公开(公告)号：US20130275829A1
公开(公告)日：2013-10-17
申请号：US13445591
申请日：2012-04-12
申请人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
发明人： Deepak Sridhara , Arvind Sridharan , Ara Patapoutian
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1048 , G11C11/5642 , H03M13/1111 , H03M13/2957 , H03M13/3707 , H03M13/6325 , H03M13/6511 , H03M13/6577
摘要： A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.
摘要翻译：用于重新使用软解码器的方法包括从存储器设备中的存储器单元接收软数据和硬数据，将软数据映射到第一组软信息，将硬数据映射到第二组软信息，并使用软解码器解码第一组和第二组软信息。

4. 发明授权

US08406051B2 Iterative demodulation and decoding for multi-page memory architecture 有权
标题翻译：用于多页存储器架构的迭代解调和解码
公开(公告)号：US08406051B2
公开(公告)日：2013-03-26
申请号：US12781780
申请日：2010-05-17
申请人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
发明人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C2029/0411
摘要： Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.
摘要翻译：访问存储在固态非易失性存储器件中的编码数据的方法和系统包括对数据进行迭代解调和解码。存储器件包括存储器单元，其被布置为存储每个存储器单元的多个位数据。存储单元能够存储多页数据。存储在存储器单元中的每个位与与存储在存储单元中的其它位相关的其它页不同的数据页相关联。响应于感测的存储器单元的电压电平对多页进行解调，并且为多页的每一页提供解调输出。生成多页的每一页的解码输出。对页面进行解码并解调多个页面进行迭代，包括解码器和解调器之间的信息交换。

5. 发明申请

US20110280068A1 JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE 有权
标题翻译：多页存储器架构中逻辑页面的编辑
公开(公告)号：US20110280068A1
公开(公告)日：2011-11-17
申请号：US12781774
申请日：2010-05-17
申请人： Ara Patapoutian , Deepak Sridhara , Bruce Buch
发明人： Ara Patapoutian , Deepak Sridhara , Bruce Buch
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C29/00 , G11C2216/14
摘要： Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.
摘要翻译：多个逻辑页面被联合编码成单个码字，并被存储在具有多层存储器单元的固态非易失性存储器（NVM）设备的相同物理页面中。多个逻辑页面的第一逻辑页面被存储在存储器设备中作为多级存储器单元的第一位，而多个逻辑页面的第二逻辑页面被临时高速缓存。在将第一逻辑页面存储为存储器单元的第一位之后，第二逻辑页面被存储为存储器单元的第二位。

6. 发明授权

US08254167B2 Joint encoding of logical pages in multi-page memory architecture 有权
标题翻译：在多页内存架构中对逻辑页进行联合编码
公开(公告)号：US08254167B2
公开(公告)日：2012-08-28
申请号：US12781774
申请日：2010-05-17
申请人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
发明人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C29/00 , G11C2216/14
摘要： Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.
摘要翻译：多个逻辑页面被联合编码成单个码字，并被存储在具有多层存储器单元的固态非易失性存储器（NVM）设备的相同物理页面中。多个逻辑页面的第一逻辑页面被存储在存储器设备中作为多级存储器单元的第一位，而多个逻辑页面的第二逻辑页面被临时高速缓存。在将第一逻辑页面存储为存储器单元的第一位之后，第二逻辑页面被存储为存储器单元的第二位。

7. 发明申请

US20110280069A1 ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE 有权
标题翻译：多媒体存储器架构的迭代解码和解码
公开(公告)号：US20110280069A1
公开(公告)日：2011-11-17
申请号：US12781780
申请日：2010-05-17
申请人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
发明人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C2029/0411
摘要： Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.
摘要翻译：访问存储在固态非易失性存储器件中的编码数据的方法和系统包括对数据进行迭代解调和解码。存储器件包括存储器单元，其被布置为存储每个存储器单元的多个位数据。存储单元能够存储多页数据。存储在存储器单元中的每个位与与存储在存储单元中的其它位相关的其它页不同的数据页相关联。响应于感测的存储器单元的电压电平对多页进行解调，并且为多页的每一页提供解调输出。生成多页的每一页的解码输出。对页面进行解码并解调多个页面进行迭代，包括解码器和解调器之间的信息交换。

8. 发明申请

US20170041099A1 Multiuse Data Channel 审中-公开
标题翻译：多用数据通道
公开(公告)号：US20170041099A1
公开(公告)日：2017-02-09
申请号：US14820137
申请日：2015-08-06
申请人： Ara Patapoutian , Hieu V. Nguyen
发明人： Ara Patapoutian , Hieu V. Nguyen
IPC分类号： H04L1/00 , H03M13/11 , G11C29/52 , H03M13/29 , G06F11/10
CPC分类号： H04L1/0045 , G06F11/1072 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/2906 , H03M13/6516 , H03M13/6561
摘要： Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.
摘要翻译：提出了具有可选组件的数据通道，例如编码器或解码器。此外，可以基于数据信号特性通过数据信道来处理具有不同数据信号特性的数据。此外，数据信道可以具有独立的编码路径和独立的解码路径。例如，具有第一数据信号特性的第一数据传输可以经由数据信道基于数据信道的第一选定组件集合进行处理，并且具有与第一数据信号特性不同的第二数据信号特性的第二数据传输可以是通过数据信道使用数据信道中的第二组选择的组来处理。第一选择的组件集合可以不同于第二选择的组件集合，但是可以共享一个或多个公共组件。

9. 发明授权

US09473266B1 Scheduling strategies for iterative decoders 有权
标题翻译：迭代解码器的调度策略
公开(公告)号：US09473266B1
公开(公告)日：2016-10-18
申请号：US12473728
申请日：2009-05-28
申请人： Ara Patapoutian , Bruce Buch , Rose Shao
发明人： Ara Patapoutian , Bruce Buch , Rose Shao
IPC分类号： G06F11/00 , H04L1/00
CPC分类号： H03M13/1111 , H03M13/1105 , H03M13/3738 , H03M13/3746 , H03M13/3784 , H03M13/616 , H03M13/6325 , H04L1/0057
摘要： An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.
摘要翻译：控制迭代解码器以通过对该块执行一个或多个解码迭代来迭代地解码块。迭代解码器使用奇偶校验矩阵，并且可以被配置为处理用于并行，顺序或并行和顺序（“混合”）奇偶校验约束更新的组合的奇偶校验矩阵。

10. 发明授权

US08760986B2 Read channel throughput management 有权
标题翻译：读取通道吞吐量管理
公开(公告)号：US08760986B2
公开(公告)日：2014-06-24
申请号：US13408849
申请日：2012-02-29
申请人： Prafulla Bollampalli Reddy , Hui Su , Michelle Elaine Blankenship , Eddie Wai Pun , John Marc Wright , Ara Patapoutian , Hieu V Nguyen
发明人： Prafulla Bollampalli Reddy , Hui Su , Michelle Elaine Blankenship , Eddie Wai Pun , John Marc Wright , Ara Patapoutian , Hieu V Nguyen
IPC分类号： G11B11/00
CPC分类号： G11B20/1217 , G11B5/09 , G11B20/10527 , G11B20/1833 , G11B2020/10759 , G11B2020/10916 , G11B2020/1232 , G11B2020/1295 , G11B2020/185
摘要： An implementation of a system disclosed herein provides a method of deferring decoding of a data sector received at a read channel of a storage device, in response to determining that a data sector cannot be decoded by a first decoder and storing the data sector for further processing by a second decoder.
摘要翻译：响应于确定数据扇区不能由第一解码器解码并存储数据扇区用于进一步处理的方法，本文公开的系统的实现提供了一种在存储设备的读取信道上推迟对数据扇区进行解码的方法通过第二解码器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式