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    • 5. 发明授权
    • Reducing energy consumption when applying body bias to substrate having sets of nand strings
    • 当将体偏置施加到具有一组n和弦的衬底时,降低能量消耗
    • US08164957B2
    • 2012-04-24
    • US13178853
    • 2011-07-08
    • Deepak Chandra SekarNima Mokhlesi
    • Deepak Chandra SekarNima Mokhlesi
    • G11C16/04
    • G11C5/146G11C16/10G11C16/26G11C2029/0409
    • Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
    • 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时,可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外,随着编程周期的增加,体偏置电平可以增加或减小。 此外,可以为芯片,平面,块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
    • 6. 发明授权
    • Non-volatile storage with adaptive body bias
    • 具有适应性偏置的非易失性存储
    • US07525843B2
    • 2009-04-28
    • US11618793
    • 2006-12-30
    • Deepak Chandra SekarNima Mokhlesi
    • Deepak Chandra SekarNima Mokhlesi
    • G11C16/00
    • G11C16/28G11C7/04G11C11/5642G11C16/0483G11C2211/565
    • A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
    • 可以应用身体偏差以优化性能的非易失性存储系统。 当从非易失性存储元件读取数据时,可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外,随着编程周期的增加,体偏置电平可以增加。 此外,可以为芯片,平面,块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
    • 7. 发明申请
    • NON-VOLATILE STORAGE WITH ADAPTIVE BODY BIAS
    • 具有自适应身体偏倚的非挥发性储存
    • US20080158992A1
    • 2008-07-03
    • US11618793
    • 2006-12-30
    • Deepak Chandra SekarNima Mokhlesi
    • Deepak Chandra SekarNima Mokhlesi
    • G11C16/06
    • G11C16/28G11C7/04G11C11/5642G11C16/0483G11C2211/565
    • A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
    • 可以应用身体偏差以优化性能的非易失性存储系统。 当从非易失性存储元件读取数据时,可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外,随着编程周期的增加,体偏置电平可以增加。 此外,可以为芯片,平面,块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。
    • 8. 发明授权
    • Reducing power consumption during read operations in non-volatile storage
    • 在非易失性存储器中读取操作期间降低功耗
    • US07606079B2
    • 2009-10-20
    • US11740091
    • 2007-04-25
    • Deepak Chandra SekarNima MokhlesiHock C. So
    • Deepak Chandra SekarNima MokhlesiHock C. So
    • G11C11/34G11C16/06
    • G11C8/08G11C11/5642G11C16/0483G11C16/26G11C2211/5646
    • Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.
    • 在读取操作期间通过在未选择的字线上提供减小的读取通过电压来减少非易失性存储设备中的功耗。 检查在其上正在读取存储元件的所选字线之后的一个或多个未选字线的编程状态,以确定未选择的字线是否包含编程的存储元件。 当识别出未编程的字线时,在该字线和在该字线之后的编程顺序中的其它字线提供减小的读通道电压。 编程状态可以通过例如存储在字线中的标志来确定,或者通过在最低读取状态下读取字线来确定。 被检查的未选择的字线可以在一组字线中预先确定,或者基于所选字线的位置自适应地确定。
    • 10. 发明申请
    • MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE
    • 基于距离的多位线路电压
    • US20090080265A1
    • 2009-03-26
    • US11861571
    • 2007-09-26
    • Nima MokhlesiDengtao ZhaoMan MuiHao NguyenSeungpil LeeDeepak Chandra SekarTapan Samaddar
    • Nima MokhlesiDengtao ZhaoMan MuiHao NguyenSeungpil LeeDeepak Chandra SekarTapan Samaddar
    • G11C16/24G11C7/12G11C16/26
    • G11C16/0483G11C7/12G11C11/5642G11C16/24G11C16/26G11C2211/5634
    • An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.
    • 非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件,连接到所选择的字线的第二组非易失性存储元件,与所选字线连接的第一组位线 第一组非易失性存储元件,与第二组非易失性存储元件通信的第二组位线,位于第一位置并连接到第一组位线的第一组感测模块, 以及位于第二位置并连接到第二组位线的第二组感测模块。 第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。 第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。