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1. 发明申请

US20200098727A1 STACKED WIRE-BOND DICE ATTACHED BY PILLARS OR BUMPS ABOVE A FLIP-CHIP DIE ON A SEMICONDUCTOR PACKAGE SUBSTRATE 审中-公开
公开(公告)号：US20200098727A1
公开(公告)日：2020-03-26
申请号：US16141415
申请日：2018-09-25
申请人： Debendra Mallik , Robert L. Sankman , Sanka Ganesan , George Vakanas , Omkar Karhade , Sri Chaitra Jyotsna Chavali , Zhaozhi George Li , Holly A. Sawyer
发明人： Debendra Mallik , Robert L. Sankman , Sanka Ganesan , George Vakanas , Omkar Karhade , Sri Chaitra Jyotsna Chavali , Zhaozhi George Li , Holly A. Sawyer
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00 , H01L23/538
摘要： A wire-bond memory die is coupled to a system-on-chip processor where the processor is flip-chip mounted on a semiconductor package substrate, and the wire-bond memory die is also flip-chip configured through a redistribution layer that pins out to a series of pillars that contact the semiconductor package substrate. The wire-bond memory die is stacked on the processor and the redistribution layer overhangs the processor to contact the series of pillars.

2. 发明申请

US20180005928A1 PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS 审中-公开
公开(公告)号：US20180005928A1
公开(公告)日：2018-01-04
申请号：US15198107
申请日：2016-06-30
申请人： Robert L. Sankman , Sanka Ganesan
发明人： Robert L. Sankman , Sanka Ganesan
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H01L21/56
CPC分类号： H01L23/49811 , H01L21/4853 , H01L21/565 , H01L23/3114 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/08238 , H01L2224/131 , H01L2224/13294 , H01L2224/133 , H01L2224/16237 , H01L2224/16238 , H01L2224/81191 , H01L2224/81192 , H01L2224/81401 , H01L2224/81411 , H01L2224/81416 , H01L2224/81438 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81473 , H01L2224/81815 , H01L2924/01004 , H01L2924/01028 , H01L2924/01029 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1532 , H01L2924/15747 , H01L2924/00014 , H01L2924/014
摘要： Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

3. 发明授权

US09368437B2 High density package interconnects 有权
标题翻译：高密度封装互连
公开(公告)号：US09368437B2
公开(公告)日：2016-06-14
申请号：US13977658
申请日：2011-12-31
申请人： Sanka Ganesan , Zhiguo Qian , Robert L. Sankman , Krishna Srinivasan , Zhaohui Zhu
发明人： Sanka Ganesan , Zhiguo Qian , Robert L. Sankman , Krishna Srinivasan , Zhaohui Zhu
IPC分类号： H01L23/498 , H01L23/00 , H01L21/768 , H01L23/50 , H01L23/538
CPC分类号： H01L23/49811 , H01L21/76885 , H01L23/50 , H01L23/5386 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/11849 , H01L2224/1301 , H01L2224/13013 , H01L2224/13014 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/13687 , H01L2224/14132 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/16013 , H01L2224/16014 , H01L2224/16058 , H01L2224/16238 , H01L2224/1703 , H01L2224/17051 , H01L2224/81191 , H01L2224/81203 , H01L2224/81385 , H01L2224/81395 , H01L2224/81411 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H01L2924/05042 , H01L2924/1434 , H01L2924/381 , H01L2924/3841 , H01L2924/014 , H01L2924/00014
摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
摘要翻译：描述了包括形成互连结构的电子组件和方法。在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。描述和要求保护其他实施例。

4. 发明申请

US20140217579A1 HIGH DENSITY PACKAGE INTERCONNECTS 有权
标题翻译：高密度封装互连
公开(公告)号：US20140217579A1
公开(公告)日：2014-08-07
申请号：US13977658
申请日：2011-12-31
申请人： Sanka Ganesan , Zhiguo Qian , Robert L. Sankman , Krishna Srinivasan , Zhaohui Zhu
发明人： Sanka Ganesan , Zhiguo Qian , Robert L. Sankman , Krishna Srinivasan , Zhaohui Zhu
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/49811 , H01L21/76885 , H01L23/50 , H01L23/5386 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/11849 , H01L2224/1301 , H01L2224/13013 , H01L2224/13014 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/13687 , H01L2224/14132 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/16013 , H01L2224/16014 , H01L2224/16058 , H01L2224/16238 , H01L2224/1703 , H01L2224/17051 , H01L2224/81191 , H01L2224/81203 , H01L2224/81385 , H01L2224/81395 , H01L2224/81411 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H01L2924/05042 , H01L2924/1434 , H01L2924/381 , H01L2924/3841 , H01L2924/014 , H01L2924/00014
摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
摘要翻译：描述了包括形成互连结构的电子组件和方法。在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。描述和要求保护其他实施例。

5. 发明申请

US20130335939A1 SHAPED AND ORIENTED SOLDER JOINTS 有权
标题翻译：形状和方向的焊接接头
公开(公告)号：US20130335939A1
公开(公告)日：2013-12-19
申请号：US13992791
申请日：2011-12-06
申请人： Aleksandar Aleksov , Sanka Ganesan
发明人： Aleksandar Aleksov , Sanka Ganesan
IPC分类号： B81B7/00
CPC分类号： B81B7/0006 , B23K35/0288 , H01L23/49816 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/1132 , H01L2224/11474 , H01L2224/11849 , H01L2224/11903 , H01L2224/13012 , H01L2224/13014 , H01L2224/13082 , H01L2224/13111 , H01L2224/1403 , H01L2224/141 , H01L2224/14135 , H01L2224/14136 , H01L2224/14177 , H01L2224/14179 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01322 , H01L2924/3511 , H05K3/3436 , H05K2201/09418 , H05K2201/10734 , H01L2924/00014 , H01L2924/00012 , H01L2924/01082 , H01L2924/01083 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
摘要： The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.
摘要翻译：本说明书涉及制造微电子组件的领域，其中微电子器件可以附接到具有多个成形和取向的焊点的微电子衬底。成形和定向的焊接接头可以是基本上椭圆形的，其中基本上椭圆形焊点的长轴可以基本上朝向微电子器件的中性点或中心定向。成形和取向的焊接接头的实施例可以减少由于应力（例如来自微电子器件和微电子衬底之间的热膨胀应力）引起的焊点故障的可能性。

6. 发明授权

US08353101B2 Method of making substrate package with through holes for high speed I/O flex cable 有权
标题翻译：制造高速I / O柔性电缆通孔的基板封装方法
公开(公告)号：US08353101B2
公开(公告)日：2013-01-15
申请号：US13008849
申请日：2011-01-18
申请人： Charan Gurumurthy , Sanka Ganesan , Chandrashekar Ramaswamy , Mark Hlad
发明人： Charan Gurumurthy , Sanka Ganesan , Chandrashekar Ramaswamy , Mark Hlad
IPC分类号： H05K3/00 , H01L21/46
CPC分类号： H01L23/48 , H01L23/49827 , H01L24/16 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K1/113 , H05K3/00 , H05K3/108 , H05K3/222 , H05K3/426 , H05K3/429 , H05K3/4602 , H05K2201/09509 , H05K2201/10189 , H05K2201/10356 , H05K2201/1053 , H05K2201/10734 , H05K2203/167 , Y10T29/49124 , H01L2224/0401
摘要： An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.
摘要翻译：与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

7. 发明授权

US08508947B2 Flex cable and method for making the same 有权
标题翻译： Flex电缆及其制作方法
公开(公告)号：US08508947B2
公开(公告)日：2013-08-13
申请号：US12896579
申请日：2010-10-01
申请人： Sanka Ganesan , Mohiuddin Mazumder , Zhichao Zhang , Kemal Aygun
发明人： Sanka Ganesan , Mohiuddin Mazumder , Zhichao Zhang , Kemal Aygun
IPC分类号： H05K1/00 , H05K7/00
CPC分类号： H05K7/00 , H05K1/181 , H05K3/28 , H05K3/282 , H05K3/361 , H05K2201/10356 , H05K2201/1053 , H05K2201/10734 , H05K2203/167 , Y02P70/611
摘要： An assembly of substrate packages interconnected with flex cables. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing detachable inter-package flex cable connection. The flex cable comprises a transmission region that includes a plurality of signal traces and a ground plane. A plurality of solder mask strips are disposed on the plurality of signals traces to provide anchoring for the signal traces. The solder mask strips intersect the signals traces. The exposed signal traces and the ground plane are coated with organic solderability preservative material. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.
摘要翻译：与柔性电缆互连的衬底封装的组件。该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。实施例涉及提供可拆卸的包装间柔性电缆连接的基板封装。柔性电缆包括包括多个信号迹线和接地平面的透射区域。多个焊接掩模条设置在多个信号迹线上以提供信号迹线的锚定。焊接掩模条与信号迹线相交。暴露的信号迹线和接地平面涂有有机可焊性防腐材料。在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

8. 发明申请

US20110108427A1 SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE 有权
标题翻译：具有高速I / O FLEX电缆的通孔的基板封装
公开(公告)号：US20110108427A1
公开(公告)日：2011-05-12
申请号：US13008849
申请日：2011-01-18
申请人： Charan Gurumurthy , Sanka Ganesan , Chandrashekar Ramaswamy , Mark Hlad
发明人： Charan Gurumurthy , Sanka Ganesan , Chandrashekar Ramaswamy , Mark Hlad
IPC分类号： C25D5/02
CPC分类号： H01L23/48 , H01L23/49827 , H01L24/16 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K1/113 , H05K3/00 , H05K3/108 , H05K3/222 , H05K3/426 , H05K3/429 , H05K3/4602 , H05K2201/09509 , H05K2201/10189 , H05K2201/10356 , H05K2201/1053 , H05K2201/10734 , H05K2203/167 , Y10T29/49124 , H01L2224/0401
摘要： An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.
摘要翻译：与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

9. 发明授权

US10903166B2 Integrated circuit packages 有权
公开(公告)号：US10903166B2
公开(公告)日：2021-01-26
申请号：US16060918
申请日：2016-01-28
申请人： Sanka Ganesan , Thorsten Meyer , Gerald Ofner , Intel IP Corporation
发明人： Sanka Ganesan , Thorsten Meyer , Gerald Ofner
IPC分类号： H01L29/40 , H01L23/532 , H01L21/66 , H01L23/538 , H01L23/00 , H01L25/065
摘要： Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

10. 发明授权

US08188594B2 Input/output package architectures 有权
标题翻译：输入/输出包体系结构
公开(公告)号：US08188594B2
公开(公告)日：2012-05-29
申请号：US12587175
申请日：2009-10-01
申请人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
发明人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
IPC分类号： H01L23/34 , H01L23/10 , H01L23/28 , H01L23/495 , H01L23/48 , H01L23/52 , H01L23/04
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

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