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1. 发明授权

US08271932B2 Hierarchical error injection for complex RAIM/ECC design 有权
标题翻译：复杂RAIM / ECC设计的分层错误注入
公开(公告)号：US08271932B2
公开(公告)日：2012-09-18
申请号：US12823010
申请日：2010-06-24
申请人： Dean G. Bair , Patrick J. Meaney , Luis A. Lastras-Montano , Alia D. Shah , Eldee Stephens
发明人： Dean G. Bair , Patrick J. Meaney , Luis A. Lastras-Montano , Alia D. Shah , Eldee Stephens
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G06F11/1008 , G06F11/108
摘要： A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.
摘要翻译：一种用于使用分层注入方案来验证RAIM / ECC设计的计算机实现的方法，所述分级注入方案包括选择用于生成错误掩码的标记，基于所选择的标记选择固定位掩码，确定是否将错误注入至少一个标记通道和至少一个通道的标记芯片; 以及当确定时将错误随机地注入所述标记通道和所述至少一个标记芯片中的至少一个中。

2. 发明申请

US20110320872A1 HIERARCHICAL ERROR INJECTION FOR COMPLEX RAIM/ECC DESIGN 有权
标题翻译：复杂RAIM / ECC设计的分层错误注入
公开(公告)号：US20110320872A1
公开(公告)日：2011-12-29
申请号：US12823010
申请日：2010-06-24
申请人： Dean G. Bair , Patrick J. Meaney , Luis A. Lastras-Montano , Alia D. Shah , Eldee Stephens
发明人： Dean G. Bair , Patrick J. Meaney , Luis A. Lastras-Montano , Alia D. Shah , Eldee Stephens
IPC分类号： G06F11/28
CPC分类号： G06F11/1008 , G06F11/108
摘要： A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.
摘要翻译：一种用于使用分层注入方案来验证RAIM / ECC设计的计算机实现的方法，所述分级注入方案包括选择用于生成错误掩码的标记，基于所选择的标记选择固定位掩码，确定是否将错误注入至少一个标记通道和至少一个通道的标记芯片; 以及当确定时将错误随机地注入所述标记通道和所述至少一个标记芯片中的至少一个中。

3. 发明申请

US20090198964A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR OUT OF ORDER INSTRUCTION ADDRESS STRIDE PREFETCH PERFORMANCE VERIFICATION 有权
标题翻译：方法，系统和计算机程序产品，用于订单指令地址纠错性能验证
公开(公告)号：US20090198964A1
公开(公告)日：2009-08-06
申请号：US12023457
申请日：2008-01-31
申请人： Wei-Yi Xiao , Dean G. Bair , Christopher A. Krygowski , Chung-Lung K. Shum
发明人： Wei-Yi Xiao , Dean G. Bair , Christopher A. Krygowski , Chung-Lung K. Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F11/3457 , G06F12/0862 , G06F2201/885 , G06F2212/6026
摘要： A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于在具有多于一个级别的高速缓存层级的处理器设计中验证无序指令地址（IA）跨步预取性能。产生多个指令流，并将指令循环回相应的指令地址。将多个指令流调度到处理器和仿真应用程序进行处理。当调度特定指令时，将特定指令的指令地址和操作数地址记录在队列中。监视处理器以确定处理器是否根据仿真应用执行提取和预取命令。检查是否为具有三个或更多步长的指令发出预取命令。

4. 发明授权

US07213122B2 Controlling the generation and selection of addresses to be used in a verification environment 失效
标题翻译：控制在验证环境中使用的地址的生成和选择
公开(公告)号：US07213122B2
公开(公告)日：2007-05-01
申请号：US10817091
申请日：2004-04-02
申请人： Dean G. Bair , Edward J. Kaminski, Jr. , James L. Schafer
发明人： Dean G. Bair , Edward J. Kaminski, Jr. , James L. Schafer
IPC分类号： G06F12/00
CPC分类号： G11C29/56 , G11C29/56004
摘要： The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be selected have been generated. Addresses are generated based on one or more defined selection attributes. The generated addresses are maintained in a database structure that also includes any attributes associated with the addresses. At least one address is selected from the database structure via a filter and forwarded to a component under test.
摘要翻译：要在验证环境中采用的地址的生成和选择紧密耦合，以确保用户希望被选择的地址已被生成。基于一个或多个定义的选择属性生成地址。生成的地址被保存在数据库结构中，该数据库结构还包括与地址相关联的任何属性。通过过滤器从数据库结构中选择至少一个地址，并将其转发到被测组件。

5. 发明授权

US06865645B1 Program store compare handling between instruction and operand caches 有权
标题翻译：程序存储在指令和操作数缓存之间的比较处理
公开(公告)号：US06865645B1
公开(公告)日：2005-03-08
申请号：US09677527
申请日：2000-10-02
申请人： Chung-Lung Kevin Shum , Dean G. Bair , Charles F. Webb , Mark A. Check , John S. Liptay
发明人： Chung-Lung Kevin Shum , Dean G. Bair , Charles F. Webb , Mark A. Check , John S. Liptay
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0848
摘要： A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
摘要翻译：一种支持包括使用包括执行单元的中央处理单元来修改多处理器系统中的后续指令的指令的程序的方法，以及指令单元和包括单独指令和操作数高速缓存的多个高速缓存。

6. 发明授权

US6119219A System serialization with early release of individual processor 失效
标题翻译：系统串行化与早期发布的单个处理器
公开(公告)号：US6119219A
公开(公告)日：2000-09-12
申请号：US70595
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F15/177 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/30101 , G06F9/3017 , G06F9/3834
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

7. 发明授权

US07996203B2 Method, system, and computer program product for out of order instruction address stride prefetch performance verification 有权
标题翻译：方法，系统和计算机程序产品，用于无序指令地址步进预取性能验证
公开(公告)号：US07996203B2
公开(公告)日：2011-08-09
申请号：US12023457
申请日：2008-01-31
申请人： Wei-Yi Xiao , Dean G. Bair , Christopher A. Krygowski , Chung-Lung K. Shum
发明人： Wei-Yi Xiao , Dean G. Bair , Christopher A. Krygowski , Chung-Lung K. Shum
IPC分类号： G06F9/44 , G06F13/10 , G06F13/12
CPC分类号： G06F9/3851 , G06F11/3457 , G06F12/0862 , G06F2201/885 , G06F2212/6026
摘要： A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于在具有多于一个级别的高速缓存层级的处理器设计中验证无序指令地址（IA）跨步预取性能。产生多个指令流，并将指令循环回相应的指令地址。将多个指令流调度到处理器和仿真应用程序进行处理。当调度特定指令时，将特定指令的指令地址和操作数地址记录在队列中。监视处理器以确定处理器是否根据仿真应用执行提取和预取命令。检查是否为具有三个或更多步长的指令发出预取命令。

8. 发明授权

US06560687B1 Method of implementing a translation lookaside buffer with support for a real space control 有权
标题翻译：实现支持实际空间控制的翻译后备缓冲器的方法
公开(公告)号：US06560687B1
公开(公告)日：2003-05-06
申请号：US09677345
申请日：2000-10-02
申请人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
发明人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the translation lookaside buffer is redefined as an Ignore Common segment bit to create new non-overlapping translation lookaside buffer entries.
摘要翻译：为了支持新的处理器控制位，在具有现有转换后备缓冲器的处理器系统中的实际空间控制（RSC）位将翻译后置缓冲器中的现有控制位，专用空间位重新定义为忽略公共段位创建新的非重叠翻译后备缓冲区条目。

9. 发明授权

US06079013A Multiprocessor serialization with early release of processors 失效
标题翻译：多处理器串行化与早期版本的处理器
公开(公告)号：US06079013A
公开(公告)日：2000-06-20
申请号：US70429
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F9/52 , G06F9/318 , G06F12/06
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3017
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

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