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1. 发明授权

US07213122B2 Controlling the generation and selection of addresses to be used in a verification environment 失效
标题翻译：控制在验证环境中使用的地址的生成和选择
公开(公告)号：US07213122B2
公开(公告)日：2007-05-01
申请号：US10817091
申请日：2004-04-02
申请人： Dean G. Bair , Edward J. Kaminski, Jr. , James L. Schafer
发明人： Dean G. Bair , Edward J. Kaminski, Jr. , James L. Schafer
IPC分类号： G06F12/00
CPC分类号： G11C29/56 , G11C29/56004
摘要： The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be selected have been generated. Addresses are generated based on one or more defined selection attributes. The generated addresses are maintained in a database structure that also includes any attributes associated with the addresses. At least one address is selected from the database structure via a filter and forwarded to a component under test.
摘要翻译：要在验证环境中采用的地址的生成和选择紧密耦合，以确保用户希望被选择的地址已被生成。基于一个或多个定义的选择属性生成地址。生成的地址被保存在数据库结构中，该数据库结构还包括与地址相关联的任何属性。通过过滤器从数据库结构中选择至少一个地址，并将其转发到被测组件。

2. 发明授权

US07483825B2 Method for the creation of a hybrid cycle simulation model 失效
标题翻译：创建混合循环模拟模型的方法
公开(公告)号：US07483825B2
公开(公告)日：2009-01-27
申请号：US11225689
申请日：2005-09-12
申请人： Gary A. Van Huben , Edward J. Kaminski, Jr. , Elspeth Anne Huston
发明人： Gary A. Van Huben , Edward J. Kaminski, Jr. , Elspeth Anne Huston
IPC分类号： F06F17/50 , G06F9/44
CPC分类号： G06F17/5022
摘要： Disclosed is a method for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation. FACDDR provides linkages for standard logic elements for abstracting one or more design interface components out of a cycle simulation environment and design interface emulation of an interface which interacts with a cycle simulation model through an API to extract present value of driving side signals of an interface and to set the cycle simulation model on the receiving side.
摘要翻译：公开了一种用于构建用于设计验证的编译数据单元（CDU）的混合周期模拟模型的方法。模拟模型可以包含针对模拟吞吐量优化的多个1周期CDU，以及针对模拟精度优化的2周期CDU或其混合。利用提取分层设计源组件的网表工具，该构造检查所有分层设计源组件的所有输入和输出是否绑定，并使用对象遍历指令将所选择的CDU合并到仿真模型中。数据管理方法用于跟踪模型中组件的有效性。另外，一个软件实体（FACDDR）允许设计组件的高带宽仿真，通常需要循环精确的模拟。 FACDDR为标准逻辑元件提供链接，用于从循环模拟环境中抽取一个或多个设计接口组件，并通过API与循环模拟模型交互的接口的设计接口仿真，以提取接口的驱动侧信号的当前值，在接收侧设置循环模拟模型。

3. 发明授权

US09378023B2 Cross-pipe serialization for multi-pipeline processor 有权
公开(公告)号：US09378023B2
公开(公告)日：2016-06-28
申请号：US13495201
申请日：2012-06-13
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Edward J. Kaminski, Jr. , Diane L. Orf
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Edward J. Kaminski, Jr. , Diane L. Orf
IPC分类号： G06F9/30 , G06F9/38 , G06F9/50 , G06F13/16 , G06F13/18 , G06F9/54 , G06F13/14
CPC分类号： G06F9/3836 , G06F9/3869 , G06F9/544 , G06F13/14 , G06F13/1605 , G06F13/1615 , G06F13/1621 , G06F13/1652 , G06F13/1657 , G06F13/1663
摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

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