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1. 发明授权

US08243866B2 Analog baud rate clock and data recovery 有权
标题翻译：模拟波特率时钟和数据恢复
公开(公告)号：US08243866B2
公开(公告)日：2012-08-14
申请号：US12116329
申请日：2008-05-07
申请人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
发明人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
IPC分类号： H04L7/00 , H04L27/06
CPC分类号： H04L7/0062
摘要： An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.
摘要翻译：模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。从第一和第二电位定时误差信号导出期望的定时误差信号。所需的定时误差信号用于确定信号采样是早还是晚。

2. 发明申请

US20090224806A1 ANALOG BAUD RATE CLOCK AND DATA RECOVERY 有权
标题翻译：模拟波特率时钟和数据恢复
公开(公告)号：US20090224806A1
公开(公告)日：2009-09-10
申请号：US12116329
申请日：2008-05-07
申请人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
发明人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
IPC分类号： H03K5/153
CPC分类号： H04L7/0062
摘要： An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.
摘要翻译：模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。从第一和第二电位定时误差信号导出期望的定时误差信号。所需的定时误差信号用于确定信号采样是早还是晚。

3. 发明申请

US20090316727A1 Real-Time Optimization of TX FIR Filter for High-Speed Data Communication 有权
标题翻译：用于高速数据通信的TX FIR滤波器的实时优化
公开(公告)号：US20090316727A1
公开(公告)日：2009-12-24
申请号：US12144610
申请日：2008-06-23
申请人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
发明人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
IPC分类号： H04J1/02
CPC分类号： H04L25/03343 , H04L7/0058
摘要： A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.
摘要翻译：定义了一个反馈模块，作为输入接收一组数据采样信号和一组参考采样信号。通过对通过FIR滤波器发送的差分信号进行采样来生成数据和参考采样信号。反馈模块被定义为对FIR滤波器的每个后光标操作相应的后光标计数器，并且基于所接收的数据集和参考采样信号来更新后光标计数器。此外，反馈模块被定义为当对应于给定抽头权重的后光标计数器的大小大于或等于阈值时，产生用于FIR滤波器的给定抽头权重的抽头权重调整信号。定义了适配模块，以将用于产生参考采样信号的参考电压调整到差分信号的状态。

4. 发明授权

US08452829B2 Real-time optimization of TX FIR filter for high-speed data communication 有权
标题翻译：实时优化TX FIR滤波器，实现高速数据通信
公开(公告)号：US08452829B2
公开(公告)日：2013-05-28
申请号：US12144610
申请日：2008-06-23
申请人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
发明人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
IPC分类号： G06F17/10
CPC分类号： H04L25/03343 , H04L7/0058
摘要： A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.
摘要翻译：定义了一个反馈模块，作为输入接收一组数据采样信号和一组参考采样信号。通过对通过FIR滤波器发送的差分信号进行采样来生成数据和参考采样信号。反馈模块被定义为对FIR滤波器的每个后光标操作相应的后光标计数器，并且基于所接收的数据集和参考采样信号来更新后光标计数器。此外，反馈模块被定义为当对应于给定抽头权重的后光标计数器的大小大于或等于阈值时，产生用于FIR滤波器的给定抽头权重的抽头权重调整信号。定义了适配模块，以将用于产生参考采样信号的参考电压调整到差分信号的状态。

5. 发明授权

US08744024B2 Clock-data recovery with non-zero h(−1) target 有权
标题翻译：具有非零h（-1）目标的时钟数据恢复
公开(公告)号：US08744024B2
公开(公告)日：2014-06-03
申请号：US13245533
申请日：2011-09-26
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
IPC分类号： H04L1/00
CPC分类号： H04L7/0054 , H04L7/0062
摘要： In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.
摘要翻译：在接收机电路中，节点接收从发射机电路传送数据的信号。此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

6. 发明申请

US20130077723A1 CLOCK-DATA RECOVERY WITH NON-ZERO h(-1) TARGET 有权
标题翻译：时钟数据恢复与非零h（-1）目标
公开(公告)号：US20130077723A1
公开(公告)日：2013-03-28
申请号：US13245533
申请日：2011-09-26
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
IPC分类号： H04L7/02
CPC分类号： H04L7/0054 , H04L7/0062
摘要： In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.
摘要翻译：在接收机电路中，节点接收从发射机电路传送数据的信号。此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

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