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1. 发明申请

US20130077723A1 CLOCK-DATA RECOVERY WITH NON-ZERO h(-1) TARGET 有权
标题翻译：时钟数据恢复与非零h（-1）目标
公开(公告)号：US20130077723A1
公开(公告)日：2013-03-28
申请号：US13245533
申请日：2011-09-26
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
IPC分类号： H04L7/02
CPC分类号： H04L7/0054 , H04L7/0062
摘要： In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.
摘要翻译：在接收机电路中，节点接收从发射机电路传送数据的信号。此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

2. 发明授权

US08744024B2 Clock-data recovery with non-zero h(−1) target 有权
标题翻译：具有非零h（-1）目标的时钟数据恢复
公开(公告)号：US08744024B2
公开(公告)日：2014-06-03
申请号：US13245533
申请日：2011-09-26
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
IPC分类号： H04L1/00
CPC分类号： H04L7/0054 , H04L7/0062
摘要： In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.
摘要翻译：在接收机电路中，节点接收从发射机电路传送数据的信号。此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

3. 发明申请

US20090316727A1 Real-Time Optimization of TX FIR Filter for High-Speed Data Communication 有权
标题翻译：用于高速数据通信的TX FIR滤波器的实时优化
公开(公告)号：US20090316727A1
公开(公告)日：2009-12-24
申请号：US12144610
申请日：2008-06-23
申请人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
发明人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
IPC分类号： H04J1/02
CPC分类号： H04L25/03343 , H04L7/0058
摘要： A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.
摘要翻译：定义了一个反馈模块，作为输入接收一组数据采样信号和一组参考采样信号。通过对通过FIR滤波器发送的差分信号进行采样来生成数据和参考采样信号。反馈模块被定义为对FIR滤波器的每个后光标操作相应的后光标计数器，并且基于所接收的数据集和参考采样信号来更新后光标计数器。此外，反馈模块被定义为当对应于给定抽头权重的后光标计数器的大小大于或等于阈值时，产生用于FIR滤波器的给定抽头权重的抽头权重调整信号。定义了适配模块，以将用于产生参考采样信号的参考电压调整到差分信号的状态。

4. 发明授权

US08452829B2 Real-time optimization of TX FIR filter for high-speed data communication 有权
标题翻译：实时优化TX FIR滤波器，实现高速数据通信
公开(公告)号：US08452829B2
公开(公告)日：2013-05-28
申请号：US12144610
申请日：2008-06-23
申请人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
发明人： Dawei Huang , Dong J. Yoon , Osman Javed , Zuxu Qin , Deqiang Song , Daniel J. Beckman , Drew G. Doblar , Waseem Ahmad , Andrew Keith Joy , Simon Dennis Forey , William Franklin Leven , Nirmal C. Warke
IPC分类号： G06F17/10
CPC分类号： H04L25/03343 , H04L7/0058
摘要： A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.
摘要翻译：定义了一个反馈模块，作为输入接收一组数据采样信号和一组参考采样信号。通过对通过FIR滤波器发送的差分信号进行采样来生成数据和参考采样信号。反馈模块被定义为对FIR滤波器的每个后光标操作相应的后光标计数器，并且基于所接收的数据集和参考采样信号来更新后光标计数器。此外，反馈模块被定义为当对应于给定抽头权重的后光标计数器的大小大于或等于阈值时，产生用于FIR滤波器的给定抽头权重的抽头权重调整信号。定义了适配模块，以将用于产生参考采样信号的参考电压调整到差分信号的状态。

5. 发明申请

US20110167297A1 CLOCK-DATA-RECOVERY TECHNIQUE FOR HIGH-SPEED LINKS 有权
标题翻译：用于高速链接的时钟数据恢复技术
公开(公告)号：US20110167297A1
公开(公告)日：2011-07-07
申请号：US12683147
申请日：2010-01-06
申请人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
发明人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： H04L7/0054 , H04L7/0062 , H04L7/0334
摘要： A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.
摘要翻译：描述接收机电路。在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样基于第二时钟信号。另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

6. 发明申请

US20100208855A1 SYSTEM AND METHOD OF ADAPTING PRECURSOR TAP COEFFICIENT 有权
标题翻译：系统和方法适应前提条纹系数
公开(公告)号：US20100208855A1
公开(公告)日：2010-08-19
申请号：US12388223
申请日：2009-02-18
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
IPC分类号： H04L7/00
CPC分类号： H04L7/0062
摘要： A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.
摘要翻译：公开了一种从输入数据信号中恢复数据的系统和方法。该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。该相位基于从数据信号恢复的时钟。响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

7. 发明授权

US08218702B2 System and method of adapting precursor tap coefficient 有权
标题翻译：适应前驱抽头系数的系统和方法
公开(公告)号：US08218702B2
公开(公告)日：2012-07-10
申请号：US12388223
申请日：2009-02-18
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
IPC分类号： H04L7/00
CPC分类号： H04L7/0062
摘要： A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.
摘要翻译：公开了一种从输入数据信号中恢复数据的系统和方法。该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。该相位基于从数据信号恢复的时钟。响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

8. 发明授权

US08155214B2 Asymmetric decision feedback equalization slicing in high speed transceivers 有权
标题翻译：高速收发器中的非对称判决反馈均衡切片
公开(公告)号：US08155214B2
公开(公告)日：2012-04-10
申请号：US12612449
申请日：2009-11-04
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L25/03878 , H04L25/03146
摘要： An asymmetric DFE receiver circuit is disclosed. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.
摘要翻译：公开了一种不对称DFE接收器电路。接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。调整速率可以根据接收到的信号是转换位还是非转换位而变化。

9. 发明申请

US20110103458A1 ASYMMETRIC DECISION FEEDBACK EQUALIZATION SLICING IN HIGH SPEED TRANSCEIVERS 有权
标题翻译：高速收发器中的不对称决策反馈均衡切换
公开(公告)号：US20110103458A1
公开(公告)日：2011-05-05
申请号：US12612449
申请日：2009-11-04
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
IPC分类号： H04L27/01 , H04L27/00 , H03K5/153
CPC分类号： H04L25/03878 , H04L25/03146
摘要： An asymmetric DFE receiver circuit. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.
摘要翻译：不对称DFE接收器电路。接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。调整速率可以根据接收到的信号是转换位还是非转换位而变化。

10. 发明授权

US08181058B2 Clock-data-recovery technique for high-speed links 有权
标题翻译：用于高速链路的时钟数据恢复技术
公开(公告)号：US08181058B2
公开(公告)日：2012-05-15
申请号：US12683147
申请日：2010-01-06
申请人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
发明人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
IPC分类号： G06F1/04 , G06F13/42 , G06F12/00 , G06F11/00 , H03L7/00 , H03K5/01 , H03K3/017 , H03K7/04 , H03K9/00 , H04L12/28 , H04J3/06 , H03H7/30 , H04B15/00 , G01R13/00 , G01R25/00 , G06K5/04 , H03M13/00
CPC分类号： H04L7/0054 , H04L7/0062 , H04L7/0334
摘要： A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.
摘要翻译：描述接收机电路。在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样基于第二时钟信号。另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

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