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1. 发明授权

US08181058B2 Clock-data-recovery technique for high-speed links 有权
标题翻译：用于高速链路的时钟数据恢复技术
公开(公告)号：US08181058B2
公开(公告)日：2012-05-15
申请号：US12683147
申请日：2010-01-06
申请人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
发明人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
IPC分类号： G06F1/04 , G06F13/42 , G06F12/00 , G06F11/00 , H03L7/00 , H03K5/01 , H03K3/017 , H03K7/04 , H03K9/00 , H04L12/28 , H04J3/06 , H03H7/30 , H04B15/00 , G01R13/00 , G01R25/00 , G06K5/04 , H03M13/00
CPC分类号： H04L7/0054 , H04L7/0062 , H04L7/0334
摘要： A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.
摘要翻译：描述接收机电路。在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样基于第二时钟信号。另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

2. 发明申请

US20100238993A1 AN INTEGRATED EQUALIZATION AND CDR ADAPTATION ENGINE WITH SINGLE ERROR MONITOR CIRCUIT 有权
标题翻译：具有单一错误监控电路的集成均衡和CDR适配发动机
公开(公告)号：US20100238993A1
公开(公告)日：2010-09-23
申请号：US12409236
申请日：2009-03-23
申请人： Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
发明人： Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L7/0337 , H04L2025/03503
摘要： A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.
摘要翻译：公开了一种数据通信系统和方法。该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。接收机使用判决反馈均衡器（DFE）和FIR来均衡接收到的数据信号。接收机采样数据信号以确定误差信号，并使用误差信号来适应FIR的前置光标抽头系数，FIR的一个或多个后置标签抽头系数，恢复时钟的相位的设置，以及 DFE的系数。为了适应设置，接收机根据在单个时钟周期内从数据信号中获取的错误样本来确定误差信号。为了确定误差信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。

3. 发明授权

US08229020B2 Integrated equalization and CDR adaptation engine with single error monitor circuit 有权
标题翻译：具有单错误监控电路的集成均衡和CDR适配引擎
公开(公告)号：US08229020B2
公开(公告)日：2012-07-24
申请号：US12409236
申请日：2009-03-23
申请人： Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
发明人： Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
IPC分类号： H04B15/00 , H04B1/10 , H03K5/159
CPC分类号： H04L25/03057 , H04L7/0337 , H04L2025/03503
摘要： A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.
摘要翻译：公开了一种数据通信系统和方法。该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。接收机使用判决反馈均衡器（DFE）和FIR来均衡接收到的数据信号。接收机采样数据信号以确定误差信号，并使用误差信号来适应FIR的前置光标抽头系数，FIR的一个或多个后置标签抽头系数，恢复时钟的相位的设置，以及 DFE的系数。为了适应设置，接收机根据在单个时钟周期内从数据信号中获取的错误样本来确定误差信号。为了确定误差信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。

4. 发明申请

US20110167297A1 CLOCK-DATA-RECOVERY TECHNIQUE FOR HIGH-SPEED LINKS 有权
标题翻译：用于高速链接的时钟数据恢复技术
公开(公告)号：US20110167297A1
公开(公告)日：2011-07-07
申请号：US12683147
申请日：2010-01-06
申请人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
发明人： Jianghui Su , Deqiang Song , Dawei Huang , Muthukumar Vairavan
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： H04L7/0054 , H04L7/0062 , H04L7/0334
摘要： A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.
摘要翻译：描述接收机电路。在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样基于第二时钟信号。另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

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