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    • 6. 发明申请
    • FPGA POWERUP TO KNOWN FUNCTIONAL STATE
    • FPGA电源到已知的功能状态
    • US20080030226A1
    • 2008-02-07
    • US11869921
    • 2007-10-10
    • Kenneth GoodnowClarence OgilvieChristopher ReynoldsJack SmithSebastian VentroneKeith Williams
    • Kenneth GoodnowClarence OgilvieChristopher ReynoldsJack SmithSebastian VentroneKeith Williams
    • H03K19/173
    • H03K19/17776H03K19/17732H03K19/17756H03K19/17772
    • A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.
    • 包括非基于非编程的默认开机电子配置的现场可编程门阵列(FPGA)设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时,FPGA器件将能够进入默认状态,而不必首先通过常规编程模式进行配置,从而在上电时节省宝贵的处理时间。 公开了几个实施例,例如掩模通孔电路,异步设置/复位电路,不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法,以减少专用于第一逻辑功能的存储器大小,以便在上电之后进一步编程。 除了节省时间和进一步的编程之外,FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。