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1. 发明申请

US20070075736A1 FPGA powerup to known functional state 失效
公开(公告)号：US20070075736A1
公开(公告)日：2007-04-05
申请号：US11371833
申请日：2006-03-09
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
IPC分类号： H03K19/177
CPC分类号： H03K19/177
摘要： A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

2. 发明申请

US20060190668A1 Computer system architecture 有权
标题翻译：计算机系统架构
公开(公告)号：US20060190668A1
公开(公告)日：2006-08-24
申请号：US11064745
申请日：2005-02-24
申请人： Giora Biran , Matthew Cushing , Robert Drehmel , Allen Gavin , Mark Kautzman , Jamie Kuesel , Ming-I Lin , David Luick , James Marcella , Mark Maxson , Eric Mejdrich , Adam Muff , Clarence Ogilvie , Charles Woodruff
发明人： Giora Biran , Matthew Cushing , Robert Drehmel , Allen Gavin , Mark Kautzman , Jamie Kuesel , Ming-I Lin , David Luick , James Marcella , Mark Maxson , Eric Mejdrich , Adam Muff , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
摘要翻译：高速计算机处理器系统具有用于图形处理器的高速接口。优选实施例将来自国际商业机器公司（IBM）的称为Giga-Processor Ultralite（GPUL）110的PowerPC微处理器与多芯片模块上的高速接口相结合。

3. 发明申请

US20060190661A1 Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer abvailability 失效
标题翻译：用于基于缓冲器可用性在总线接口处控制转发或终止请求的方法和系统
公开(公告)号：US20060190661A1
公开(公告)日：2006-08-24
申请号：US11064570
申请日：2005-02-24
申请人： Clarence Ogilvie , Charles Woodruff
发明人： Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F12/0831
摘要： A bus bridge for coupling between a first bus and a second bus includes: a number of data buffers for a particular request type; a counter for monitoring a number of requests of the particular type received at the bus bridge from the first bus for access to the second bus; and override logic. Each request of the particular type requires one data buffer of the number of data buffers for the particular request type. The override logic determines when the monitored number of requests of the particular type exceeds the number of data buffers for the particular request type at the bus bridge, and responsive thereto, initiates a request termination signal at the bus bridge to terminate a received request of the particular type. When request coherency is maintained employing snooping, the request termination signal is a retry snoop response signal output from the bus bridge.
摘要翻译：用于在第一总线和第二总线之间耦合的总线桥包括：用于特定请求类型的多个数据缓冲器; 一个计数器，用于监视从第一总线在总线桥接收到的特定类型的多个请求以访问第二总线; 并覆盖逻辑。特定类型的每个请求需要用于特定请求类型的数据缓冲器数量的一个数据缓冲器。覆盖逻辑确定何时监视的特定类型的请求数量超过了总线桥上特定请求类型的数据缓冲器的数量，并响应于此，在总线桥上发起请求终止信号以终止接收到的请求特定类型。当采用窥探保持请求一致性时，请求终止信号是从总线桥输出的重试监听响应信号。

4. 发明申请

US20060190655A1 Apparatus and method for transaction tag mapping between bus domains 审中-公开
标题翻译：总线域之间交易标签映射的装置和方法
公开(公告)号：US20060190655A1
公开(公告)日：2006-08-24
申请号：US11064567
申请日：2005-02-24
申请人： Mark Kautzman , Clarence Ogilvie , Charles Woodruff
发明人： Mark Kautzman , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： An apparatus and method to provide tag mapping between bus domains across a bus bridge. The preferred embodiments provide a simple tag mapping design while maintaining unique IDs for all outstanding transactions for an overall increase in computer system performance. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI bus). In preferred embodiments, the transaction mapping logic ensures that transactions generated by any logical unit (CPU) appear to originate from a single logical unit.
摘要翻译：一种通过总线桥提供总线域之间的标签映射的装置和方法。优选实施例提供简单的标签映射设计，同时为所有未完成的事务维护唯一的ID，以便计算机系统性能的总体增加。优选实施例是用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与输出高速接口（MPI总线）之间的总线桥。在优选实施例中，事务映射逻辑确保由任何逻辑单元（CPU）生成的事务似乎源于单个逻辑单元。

5. 发明申请

US20050125760A1 Data processing in digital systems 失效
标题翻译：数字系统中的数据处理
公开(公告)号：US20050125760A1
公开(公告)日：2005-06-09
申请号：US10729750
申请日：2003-12-04
申请人： Kenneth Goodnow , Clarence Ogilvie , Sebastian Ventrone
发明人： Kenneth Goodnow , Clarence Ogilvie , Sebastian Ventrone
IPC分类号： G06F15/177 , G06F15/78 , G06F17/50 , H01L25/00 , H03K19/177
CPC分类号： G06F17/5054 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.
摘要翻译：包括用于缓解瓶颈的FPGA（现场可编程门阵列）的结构以及用于操作该结构的方法。 FPGA包括多个FPGA元件，每个FPGA元件包括CLB（可配置逻辑块），指令队列和数据缓冲器。可以通过第一本地IO（输入/输出）电路在FPGA中形成一个功能块（彼此分开）并移动到第二个本地IO电路。在每个功能块内，映射的逻辑位置函数计算从存储在映射位置寄存器中的功能块的当前位置以及存储在映射的目的地寄存器中的目的地的步长的方向，距离和时间，以及时间允许移动，并将步进的方向和距离存储在映射运动寄存器中。然后，功能块根据存储在映射运动寄存器中的方向和距离移动。

6. 发明申请

US20050001280A1 CIRCUIT AND METHOD FOR PIPELINED INSERTION 失效
标题翻译：用于管道插入的电路和方法
公开(公告)号：US20050001280A1
公开(公告)日：2005-01-06
申请号：US10604205
申请日：2003-07-01
申请人： Robert Horton , David Milton , Clarence Ogilvie , Paul Schanely , Sebastian Ventrone
发明人： Robert Horton , David Milton , Clarence Ogilvie , Paul Schanely , Sebastian Ventrone
IPC分类号： G06F13/42 , H01L31/107 , H04L25/14
CPC分类号： G06F13/4247 , H04L25/14
摘要： The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line
摘要翻译：本发明通过首先沿着分段数据线的第一段传播第一数据部分，然后沿着分段数据线的第二段传播第一数据部分并同时沿第二数据部分传播第二数据部分分段数据线的第一段。本发明将单个数据传输中断到这样的不同数据部分，并且随后将所有不同数据部分已经沿着分段数据线的所有部分单独发送，将不同的数据部分重新组合成单个数据传输

7. 发明申请

US20080024197A1 METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE 有权
标题翻译：电子设备电源管理的方法和架构
公开(公告)号：US20080024197A1
公开(公告)日：2008-01-31
申请号：US11846578
申请日：2007-08-29
申请人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Keith Williams , Sebastian Ventrone
发明人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Keith Williams , Sebastian Ventrone
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , G06F1/3287 , H01L25/16 , H01L28/60 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/19105 , Y02D10/171 , H01L2224/0401
摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.
摘要翻译：一种降低低功率电子设备中的静态功耗的方法。所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的对应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

8. 发明申请

US20070198808A1 PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS 有权
标题翻译：处理器管道结构逻辑状态保持系统和方法
公开(公告)号：US20070198808A1
公开(公告)日：2007-08-23
申请号：US11276236
申请日：2006-02-20
申请人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Keith Williams
发明人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Keith Williams
IPC分类号： G06F15/00
CPC分类号： G06F9/3869 , G11C27/026
摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译：公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。比较器位于处理器流水线架构的两个阶段之间。存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。提供了与早期输出值相同的参考逻辑。逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态电容器。提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

9. 发明申请

US20070162792A1 METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES 失效
标题翻译：增加可编程逻辑器件制造工艺的方法
公开(公告)号：US20070162792A1
公开(公告)日：2007-07-12
申请号：US11275536
申请日：2006-01-12
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Paul Zuchowski
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Paul Zuchowski
IPC分类号： G01R31/26 , G11C29/00
CPC分类号： G01R31/31718 , G11C17/14 , G11C29/88 , H03K19/17764 , H03K19/17796
摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.
摘要翻译：一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

10. 发明申请

US20060190667A1 Pipeline bit handling circuit and method for a bus bridge 失效
标题翻译：一种总线桥管道位处理电路及方法
公开(公告)号：US20060190667A1
公开(公告)日：2006-08-24
申请号：US11064744
申请日：2005-02-24
申请人： Robert Drehmel , Clarence Ogilvie , Charles Woodruff
发明人： Robert Drehmel , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F12/0831
摘要： A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier. In a bus domain where pipeline transactions are allowed if the P-Bit is asserted and are not allowed if the P-Bit is not asserted, embodiments herein allow a master bus device to ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. The required separation for P=0 commands is maintained within the bus bridge. In the preferred embodiments, the separation between P=0 commands is maintained by immediately retrying P=0 commands rather than spacing snoop requests.
摘要翻译：一种用于在两条不同总线之间的总线桥上提供流水线位处理的电路和方法。在优选实施例中，流水线位处理电路为P位地址修改器具有不同规则的两个不同总线之间的总线桥上的P位地址修改器提供规则强制。在一个总线域中，如果P位被断言，允许流水线事务被允许，并且如果P位不被置位则不允许流水线事务，这里的实施例允许主总线设备确保所有总线设备将看到P = 0命令，与任何其他P = 0命令的定义的最小间距。在总线桥内保持P = 0命令所需的间隔。在优选实施例中，通过立即重试P = 0命令而不是间隔窥探请求来保持P = 0命令之间的间隔。

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