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1. 发明授权

US4866728A Electric discharge apparatus 失效
标题翻译：放电装置
公开(公告)号：US4866728A
公开(公告)日：1989-09-12
申请号：US166381
申请日：1988-02-04
申请人： David R. Evans , John E. Harry
发明人： David R. Evans , John E. Harry
IPC分类号： H01S3/038
CPC分类号： H01S3/038 , H01S3/0381
摘要： A gas laser includes a laser cavity, mirror means defining an optical path in the cavity, electrodes defining an electric discharge path in the cavity, the electrodes including at least one anode member having a passage therethrough which at one end opens into the cavity, and gas supply means for injecting gas into the cavity through the passage, wherein the wall of the passage at said one end and the exterior of the anode member around the end of said passage is electrically insulated and an electrically conducting anode surface defining the root of the discharge is provided inwardly of the perimeter of the open end of the passage.
摘要翻译：气体激光器包括激光腔，在空腔中限定光路的反射镜装置，限定空腔中的放电路径的电极，所述电极包括至少一个具有穿过其中的通道的阳极部件，其一端通向腔体，以及用于通过通道将气体注入空腔的气体供应装置，其中围绕所述通道端部的所述一端的所述通道的壁和所述阳极构件的外部是电绝缘的，并且限定所述通道的根部的导电阳极表面在通道的开口端的周边的内侧设置放电。

2. 发明申请

US20120302743A1 Long Wavelength Absorbing Porphyrin Photosensitizers for Dye-Sensitized Solar Cells 有权
标题翻译：用于染料敏化太阳能电池的长波长吸收卟啉光敏剂
公开(公告)号：US20120302743A1
公开(公告)日：2012-11-29
申请号：US13117529
申请日：2011-05-27
申请人： Sean Andrew Vail , David R. Evans , Wei Pan
发明人： Sean Andrew Vail , David R. Evans , Wei Pan
IPC分类号： C07D487/22
CPC分类号： C07D487/22 , Y02E10/542
摘要： A long wavelength absorbing porphyrin/metalloporphyrin molecule is provided, made up of a porphyrin macrocycle and an anchor group for attachment to a substrate. A molecular linking element is interposed between the porphyrin macrocycle and the anchor group. The porphyrin/metalloporphyrin molecule also includes an (aminophenyl)amine group, either N,N-(4-aminophenyl)amine or N-phenyl-N-(4-aminophenyl)amine, where an amino moiety of the 4-aminophenyl group is derivatized by an element such as hydrogen, haloalkanes, aromatic hydrocarbons, halogenated aromatic hydrocarbons, heteroarenes, halogenated heteroarenes, or combinations of the above-mentioned elements.
摘要翻译：提供长波长吸收卟啉/金属卟啉分子，其由卟啉大环化合物和锚定基团组成，用于附着于基底。分子连接元件介于卟啉大环和锚基之间。卟啉/金属卟啉分子还包括（氨基苯基）胺基团，N，N-（4-氨基苯基）胺或N-苯基-N-（4-氨基苯基）胺，其中4-氨基苯基的氨基部分为由诸如氢，卤代烷烃，芳族烃，卤代芳烃，杂芳烃，卤代杂芳烃或上述元素的组合的元素衍生。

3. 发明授权

US07968419B2 Back-to-back metal/semiconductor/metal (MSM) Schottky diode 有权
标题翻译：背对背金属/半导体/金属（MSM）肖特基二极管
公开(公告)号：US07968419B2
公开(公告)日：2011-06-28
申请号：US12234663
申请日：2008-09-21
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

4. 发明授权

US07267996B2 Iridium etching for FeRAM applications 失效
标题翻译：用于FeRAM应用的铱蚀刻
公开(公告)号：US07267996B2
公开(公告)日：2007-09-11
申请号：US10923165
申请日：2004-08-20
申请人： Fengyan Zhang , David R. Evans , Wei Pan , Lisa H. Stecker , Jer-Shen Maa
发明人： Fengyan Zhang , David R. Evans , Wei Pan , Lisa H. Stecker , Jer-Shen Maa
IPC分类号： H01L21/467
CPC分类号： H01L21/32136 , H01L21/28291
摘要： A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the hard mask; etching the hard mask layer; etching the iridium layer using argon, oxygen and chlorine chemistry in a high-density plasma reactor; and completing the ferroelectric device.
摘要翻译：蚀刻用于铁电体器件的铱层的方法包括：制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积铱层; 在铱层上沉积硬掩模层; 在硬掩模上沉积，图案化和显影光致抗蚀剂层; 蚀刻硬掩模层; 在高密度等离子体反应器中使用氩，氧和氯化学蚀刻铱层; 并完成铁电器件。

5. 发明授权

US07029982B1 Method of affecting RRAM characteristics by doping PCMO thin films 有权
标题翻译：通过掺杂PCMO薄膜影响RRAM特性的方法
公开(公告)号：US07029982B1
公开(公告)日：2006-04-18
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

6. 发明授权

US06951825B2 Method of etching a SiN/Ir/TaN or SiN/Ir/Ti stack using an aluminum hard mask 失效
标题翻译：使用铝硬掩模蚀刻SiN / Ir / TaN或SiN / Ir / Ti叠层的方法
公开(公告)号：US06951825B2
公开(公告)日：2005-10-04
申请号：US10391294
申请日：2003-03-17
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/32139 , H01L28/65
摘要： A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.
摘要翻译：蚀刻方法包括准备基板; 沉积第一蚀刻停止层; 形成铱底电极层; 沉积SiN层; 沉积和图案化铝硬掩模; 用SiN选择性蚀刻剂蚀刻未图案化的SiN层，停止在铱底部电极层的水平面上; 用第二选择性蚀刻剂蚀刻第一蚀刻停止层; 将氧化物层沉积并将所述氧化物层CMP沉积到剩余SiN层的水平; 湿式蚀刻SiN层以形成沟槽; 在通过去除SiN层形成的沟槽中沉积一层铁电材料; 沉积一层高K氧化物; 并完成设备，包括金属化。

7. 发明授权

US06627510B1 Method of making self-aligned shallow trench isolation 有权
标题翻译：自对准浅沟槽隔离方法
公开(公告)号：US06627510B1
公开(公告)日：2003-09-30
申请号：US10112014
申请日：2002-03-29
申请人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
发明人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
IPC分类号： H01L21762
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L29/517 , H01L29/518 , Y10S438/975
摘要： A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.
摘要翻译：提供了一种改进的STI工艺，包括在衬底上形成第一多晶硅层。通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部层。然后可以使用CMP工艺将得到的结构平坦化。可以通过选择性地蚀刻氧化物层来形成对准键。然后可以使用光致抗蚀剂沉积和图案化第三多晶硅层以形成栅极结构。在图案化期间，蚀刻暴露的第二多晶硅层。在完成去除第二多晶硅层时检测到蚀刻停止。保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。

8. 发明授权

US06281377B1 Substituted cycloalkene new copper precursors for chemical vapor deposition of copper metal thin films 有权
标题翻译：用于铜金属薄膜化学气相沉积的取代的环烯烃新铜前体
公开(公告)号：US06281377B1
公开(公告)日：2001-08-28
申请号：US09502425
申请日：2000-02-11
申请人： Wei-Wei Zhuang , Tue Nguyen , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , Tue Nguyen , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
IPC分类号： C07F108
CPC分类号： C23C16/18 , C07F1/08
摘要： A method of forming a volatile copper precursor for chemical vapor deposition of copper metal thin film includes formation of a volatile liquid having a chemical formula of (n-R-m-cyclohexene)Cu(I)(hfac) or (n-R-m-cyclopentene)Cu(I)(hfac), where n,m=1-6, and where R is a alkyl, such as methyl and ethyl.
摘要翻译：形成铜金属薄膜的化学气相沉积挥发性铜前体的方法包括形成化学式为（nRm-环己烯）Cu（I）（hfac）或（nRm-环戊烯）Cu（I）的挥发性液体，（hfac），其中n，m = 1-6，其中R是烷基，例如甲基和乙基。

9. 发明授权

US5939334A System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides 失效
标题翻译：选择性地清洗铜基板表面的系统和方法，原位去除铜氧化物
公开(公告)号：US5939334A
公开(公告)日：1999-08-17
申请号：US861808
申请日：1997-05-22
申请人： Tue Nguyen , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
发明人： Tue Nguyen , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
IPC分类号： C23F1/12 , C23G5/00 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/768
CPC分类号： C23G5/00 , H01L21/02063 , H01L21/31111 , H01L21/31138 , H01L21/32134 , H01L21/76838 , H01L21/02068
摘要： A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided. The method removes metal oxides with .beta.-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed. An IC having a metal interconnection, in which the underlying copper layer is cleaned of copper oxides, in-situ with Hhfac vapor, is also provided.
摘要翻译：提供了一种选择性地蚀刻不含铜氧化物的铜表面以准备沉积互连金属材料的系统和方法。该方法用β-二酮如Hhfac除去金属氧化物。 Hhfac以蒸气形式输送到系统中，几乎完全与铜氧化物反应。清洁过程的副产物同样是挥发性的，用于在真空压力下从系统中除去。由于该方法很容易适用于大多数IC工艺系统，所以它可以在无氧环境下进行，而不会从处理室中移除IC。在沉积互连金属之前，原位清洁工艺允许最小量的氧化铜重整。以这种方式，形成铜表面和互连金属材料之间的高导电性电互连。还提供了具有金属互连的IC，其中下面的铜层用Hhfac蒸气原位清除了铜氧化物。

10. 发明授权

US07714354B2 Electroformed metal structure 有权
标题翻译：电铸金属结构
公开(公告)号：US07714354B2
公开(公告)日：2010-05-11
申请号：US11978909
申请日：2007-10-30
申请人： David R. Evans , John W. Hartzell
发明人： David R. Evans , John W. Hartzell
IPC分类号： H01L29/80
CPC分类号： H01L21/288 , C23C18/1605 , C23C18/165 , C23C18/1657 , C25D1/003 , C25D5/022 , C25D5/50 , H01L21/2885 , H01L21/76885
摘要： A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).
摘要翻译：提供了一种电铸金属集成电路结构的方法。该方法包括：通过层间绝缘体形成诸如通孔或线的开口，暴露衬底表面; 形成覆盖层间绝缘体和衬底表面的基层; 形成覆盖基层的冲击层; 形成覆盖所述冲击层的顶层; 选择性蚀刻以去除覆盖在衬底表面上的顶层，暴露出一层击打层表面; 并且电铸在覆盖着撞击层表面的金属结构。使用电镀或无电沉积工艺沉积电铸金属结构。通常，金属是Cu，Au，Ir，Ru，Rh，Pd，Os，Pt或Ag。可以使用物理气相沉积（PVD），蒸发，反应溅射或金属有机化学气相沉积（MOCVD）来沉积基底，打击和顶层。

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