专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5831925A Memory configuration circuit and method 失效
标题翻译：内存配置电路和方法
公开(公告)号：US5831925A
公开(公告)日：1998-11-03
申请号：US982672
申请日：1997-12-02
申请人： David R. Brown , Shoji Wada , Kazuya Ito , Yasuhito Ichimura , Ken Saitoh
发明人： David R. Brown , Shoji Wada , Kazuya Ito , Yasuhito Ichimura , Ken Saitoh
IPC分类号： G11C11/41 , G06F12/06 , G11C7/10 , G11C8/12 , G11C11/401 , G11C8/00 , G11C7/00
CPC分类号： G11C8/12 , G11C7/1045
摘要： A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality. For example, the array may originally be arranged in four banks, but by the placing the proper signal at the input of the bond option circuit, the array is selectable as a two-bank array.
摘要翻译：存储器电路包括具有输入和输出的接合选择电路106，以及耦合到接合选择电路的输出的行控制电路100，行控制电路包括地址端子A12和A13。存储器电路还包括耦合到键选择电路的输出的列控制电路102，列控制电路102还包括地址端子A12和A13。存储单元阵列耦合到行控制和列控制电路，并且被布置在第一多个存储单元组中，这些存储体可以由行控制和列控制电路的地址端上的地址信号的组合来选择。响应于接合选择电路106的输入处的第一信号，接合选择电路在耦合到行控制器100和列控制器102电路的接合选择电路的输出处产生第二信号。响应于第二信号，行控制和列控制电路使得阵列的组可选择在第二组中。例如，阵列最初可以排列成四个组，但是通过将适当的信号放置在键合选项电路的输入处，阵列可以选择为双组阵列。

2. 发明授权

US5892726A Address decoder 失效
标题翻译：地址解码器
公开(公告)号：US5892726A
公开(公告)日：1999-04-06
申请号：US721294
申请日：1996-09-26
申请人： Yoojoon Moon , Shunichi Sukegawa , Yasuhito Ichimura , Makoto Saeki
发明人： Yoojoon Moon , Shunichi Sukegawa , Yasuhito Ichimura , Makoto Saeki
IPC分类号： G11C11/413 , G11C8/10 , G11C11/408 , G11C8/00
CPC分类号： G11C8/10 , G11C11/4087
摘要： An address decoder with low power consumption of feedthrough current, leakage current, etc. Address bits AY0.sub.0 -AY0.sub.7 are respectively supplied to n-type gate terminals of CMOS transfer gates C.sub.0 -C.sub.7 and the gate terminals of PMOS transistors P.sub.0 -P.sub.7. Inverted address bits AY0.sub.0- -AY0.sub.7- are supplied to p-type gate terminals of the CMOS transfer gates C.sub.0 -C.sub.7. Enable signals AY3.sub.p, AY6.sub.q are respectively input to both input terminals of a NAND circuit 10. The output terminals of NAND circuit 10 are connected to the input terminals of CMOS transfer gates C.sub.0 -C.sub.7. The output terminals of CMOS transfer gates C.sub.0 -C.sub.7 are connected to the input terminals of the drivers D.sub.0 -D.sub.7 and the drain terminals of the PMOS transistors P.sub.0 -P.sub.7 via a node F.sub.0 -F.sub.7. The source terminals of PMOS transistors P.sub.0 -P.sub.7 are connected to a power supply voltage V.sub.cc, for example of 3.3 V. The output terminals of drivers D.sub.0 -D.sub.7 are connected to Y-address lines YS.sub.0 -YS.sub.7.
摘要翻译：具有低通电电流，漏电流等功耗的地址解码器。地址位AY00-AY07分别提供给CMOS传输门C0-C7的n型栅极端子和PMOS晶体管P0-P7的栅极端子。反向地址位AY00 - AY07-被提供给CMOS传输门C0-C7的p型栅极端子。分别向NAND电路10的两个输入端子输入使能信号AY3p，AY6q。NAND电路10的输出端子与CMOS转移门C0-C7的输入端子连接。 CMOS传输门C0-C7的输出端通过节点F0-F7连接到驱动器D0-D7的输入端和PMOS晶体管P0-P7的漏极端子。 PMOS晶体管P0-P7的源极端子连接到例如3.3V的电源电压Vcc。驱动器D0-D7的输出端子连接到Y地址线YS0-YS7。

3. 发明授权

US06373745B2 Semiconductor memory cell and semiconductor memory device 有权
标题翻译：半导体存储单元和半导体存储器件
公开(公告)号：US06373745B2
公开(公告)日：2002-04-16
申请号：US09813530
申请日：2001-03-21
申请人： Yoritaka Saito , Hiroshi Ikeda , Takumi Nasu , Kohsuke Ikeda , Yoshinobu Matsumoto , Satoshi Nakayama , Yasuhito Ichimura
发明人： Yoritaka Saito , Hiroshi Ikeda , Takumi Nasu , Kohsuke Ikeda , Yoshinobu Matsumoto , Satoshi Nakayama , Yasuhito Ichimura
IPC分类号： G11C1134
CPC分类号： G11C11/412
摘要： The objective of this invention is to reduce the layout area while guaranteeing data retention stability in a static type semiconductor memory cell. This SRAM cell is constituted with two MOS transistors 10 and 12 and one inverter circuit 14. The source terminal of PMOS transistor 10 is connected to bit line (BL), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to word line (WL). The source tenninal of NMOS transistor 12 is connected to a supply voltage terminal that provides low-level reference potential VSS (for example, zero volts), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to the output terminal o inverter circuit 14. The input terminal of inverter circuit 14 is connected to data storage node (Na).
摘要翻译：本发明的目的是在保证静态型半导体存储单元中的数据保持稳定性的同时减小布局面积。该SRAM单元由两个MOS晶体管10和12以及一个反相器电路14构成。PMOS晶体管10的源极端子连接到位线（BL），漏极端子连接到数据存储节点（Na），栅极终端连接到字线（WL）。 NMOS晶体管12的源极连接到提供低电平参考电位VSS（例如，零伏特）的电源电压端子，漏极端子连接到数据存储节点（Na），并且栅极端子连接到输出端子o逆变器电路14.逆变器电路14的输入端子连接到数据存储节点（Na）。

4. 发明授权

US5140182A Plural stage voltage booster circuit with efficient electric charge transfer between successive stages 失效
标题翻译：多级电压升压电路，具有连续阶段之间有效的电荷转移
公开(公告)号：US5140182A
公开(公告)日：1992-08-18
申请号：US521793
申请日：1990-05-10
申请人： Yasuhito Ichimura
发明人： Yasuhito Ichimura
IPC分类号： G11C14/00 , G11C5/14 , H02M3/07
CPC分类号： G11C5/145 , H02M3/073
摘要： Electric charge transmit elements (QD) transmit electric charge from a terminal side (NA) to a control electrode side (NB) of the circuit. The voltage at the control electrode side (NB) is raised by a capacitor configuration (CB). Voltage stabilizing elements (QC) are connected in parallel to the electric charge transmit elements between the terminal side and the control electrode side. In transferring the electric charge from the control electrode side (NB) to the other terminal side (NC), the voltage at the control electrode side (NB) is kept higher than the other terminal side (NC). Therefore, because loss of voltage by the electric charge transfer elements (QB) in transferring the electric charge is eliminated, a predetermined voltage is obtained efficiently in a short time, and a highly reliable booster circuit is provided.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式