专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5892726A Address decoder 失效
标题翻译：地址解码器
公开(公告)号：US5892726A
公开(公告)日：1999-04-06
申请号：US721294
申请日：1996-09-26
申请人： Yoojoon Moon , Shunichi Sukegawa , Yasuhito Ichimura , Makoto Saeki
发明人： Yoojoon Moon , Shunichi Sukegawa , Yasuhito Ichimura , Makoto Saeki
IPC分类号： G11C11/413 , G11C8/10 , G11C11/408 , G11C8/00
CPC分类号： G11C8/10 , G11C11/4087
摘要： An address decoder with low power consumption of feedthrough current, leakage current, etc. Address bits AY0.sub.0 -AY0.sub.7 are respectively supplied to n-type gate terminals of CMOS transfer gates C.sub.0 -C.sub.7 and the gate terminals of PMOS transistors P.sub.0 -P.sub.7. Inverted address bits AY0.sub.0- -AY0.sub.7- are supplied to p-type gate terminals of the CMOS transfer gates C.sub.0 -C.sub.7. Enable signals AY3.sub.p, AY6.sub.q are respectively input to both input terminals of a NAND circuit 10. The output terminals of NAND circuit 10 are connected to the input terminals of CMOS transfer gates C.sub.0 -C.sub.7. The output terminals of CMOS transfer gates C.sub.0 -C.sub.7 are connected to the input terminals of the drivers D.sub.0 -D.sub.7 and the drain terminals of the PMOS transistors P.sub.0 -P.sub.7 via a node F.sub.0 -F.sub.7. The source terminals of PMOS transistors P.sub.0 -P.sub.7 are connected to a power supply voltage V.sub.cc, for example of 3.3 V. The output terminals of drivers D.sub.0 -D.sub.7 are connected to Y-address lines YS.sub.0 -YS.sub.7.
摘要翻译：具有低通电电流，漏电流等功耗的地址解码器。地址位AY00-AY07分别提供给CMOS传输门C0-C7的n型栅极端子和PMOS晶体管P0-P7的栅极端子。反向地址位AY00 - AY07-被提供给CMOS传输门C0-C7的p型栅极端子。分别向NAND电路10的两个输入端子输入使能信号AY3p，AY6q。NAND电路10的输出端子与CMOS转移门C0-C7的输入端子连接。 CMOS传输门C0-C7的输出端通过节点F0-F7连接到驱动器D0-D7的输入端和PMOS晶体管P0-P7的漏极端子。 PMOS晶体管P0-P7的源极端子连接到例如3.3V的电源电压Vcc。驱动器D0-D7的输出端子连接到Y地址线YS0-YS7。

IPRDB

热门服务

关于我们

友情链接

联系方式