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1. 发明授权

US07619455B2 Digital single event transient hardened register using adaptive hold 有权
标题翻译：数字单事件瞬态硬化寄存器采用自适应保持
公开(公告)号：US07619455B2
公开(公告)日：2009-11-17
申请号：US11737225
申请日：2007-04-19
申请人： Roy M. Carlson , David O. Erstad
发明人： Roy M. Carlson , David O. Erstad
IPC分类号： H03K3/356
CPC分类号： H03K19/007 , G11C5/005 , H03K3/0375 , H03K3/3562 , H03K5/1534 , H03K5/19
摘要： By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.
摘要翻译：通过调整寄存器的捕获时钟边沿定时，使得当数据返回到正确状态时，寄存器捕获数据，寄存器可能受到保护，防止DSET发生故障。如果在时钟沿附近发生数据毛刺，则寄存器输出的有效时间增加（CLK至Q）。当在时钟边缘附近检测到DSET瞬态的存在时，会出现这种有效的时间增加。

2. 发明授权

US07451384B2 Error recovery in asynchronous combinational logic circuits 失效
标题翻译：异步组合逻辑电路中的错误恢复
公开(公告)号：US07451384B2
公开(公告)日：2008-11-11
申请号：US10891654
申请日：2004-07-15
申请人： David O. Erstad , Roy M. Carlson
发明人： David O. Erstad , Roy M. Carlson
IPC分类号： G06F11/08
CPC分类号： H03K19/23 , H03K19/00392
摘要： A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.
摘要翻译：提出了一种向异步逻辑电路提供错误恢复的系统和方法。具有错误恢复的异步逻辑电路可以使用时间冗余来比较异步计算的结果并且如果需要的话启动错误恢复。使用多个异步寄存器选择器来比较异步逻辑电路的输出。如果异步寄存器选择器检测到不一致的结果，则异步寄存器选择器将自动清除。来自多个异步寄存器选择器的大多数公共数据输出被提供为表示异步逻辑电路的输出的输出。

3. 发明授权

US06791362B1 System level hardening of asynchronous combinational logic 失效
标题翻译：异步组合逻辑的系统级硬化
公开(公告)号：US06791362B1
公开(公告)日：2004-09-14
申请号：US10731387
申请日：2003-12-09
申请人： Roy M. Carlson , David O. Erstad
发明人： Roy M. Carlson , David O. Erstad
IPC分类号： H03K1900
CPC分类号： G06F11/00
摘要： A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two asynchronous registers. A fault detector is used to detect a fault at an output of the asynchronous combinational logic circuit caused by SEU. If the fault detector detects a fault, a first asynchronous register is prevented from clearing stored data and a second asynchronous register is prevented from loading data from the asynchronous combinational logic circuit until the fault is cleared. Further, a timer circuit is used to ensure enough time elapses to allow the asynchronous combinational logic circuit to reevaluate itself. The asynchronous combinational logic circuit reevaluates itself by first propagating a NULL wave front to clear the fault and then propagating the data stored in the first asynchronous register to its outputs.
摘要翻译：提出了一种用于强化针对单事件颠簸（SEU）的异步组合逻辑电路的系统和方法。异步组合逻辑电路位于两个异步寄存器之间。故障检测器用于检测由SEU引起的异步组合逻辑电路的输出故障。如果故障检测器检测到故障，则防止第一异步寄存器清除存储的数据，并且防止第二异步寄存器从异步组合逻辑电路加载数据，直到故障被清除。此外，定时器电路用于确保足够的时间经过以允许异步组合逻辑电路重新评估其自身。异步组合逻辑电路通过首先传播NULL波前来清除故障，然后将存储在第一异步寄存器中的数据传播到其输出来重新评估自身。

4. 发明申请

US20080258792A1 Digital Single Event Transient Hardened Register Using Adaptive Hold 有权
标题翻译：使用自适应保持的数字单事件瞬态硬化寄存器
公开(公告)号：US20080258792A1
公开(公告)日：2008-10-23
申请号：US11737225
申请日：2007-04-19
申请人： Roy M. Carlson , David O. Erstad
发明人： Roy M. Carlson , David O. Erstad
IPC分类号： G06F1/04
CPC分类号： H03K19/007 , G11C5/005 , H03K3/0375 , H03K3/3562 , H03K5/1534 , H03K5/19
摘要： By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.
摘要翻译：通过调整寄存器的捕获时钟边沿定时，使得当数据返回到正确状态时，寄存器捕获数据，寄存器可能受到保护，防止DSET发生故障。如果在时钟沿附近发生数据毛刺，则寄存器输出的有效时间增加（CLK至Q）。当在时钟边缘附近检测到DSET瞬态的存在时，会出现这种有效的时间增加。

5. 发明授权

US06937053B2 Single event hardening of null convention logic circuits 失效
标题翻译：零常规逻辑电路的单事件加固
公开(公告)号：US06937053B2
公开(公告)日：2005-08-30
申请号：US10463794
申请日：2003-06-17
申请人： Roy M. Carlson , David O. Erstad
发明人： Roy M. Carlson , David O. Erstad
IPC分类号： H03K19/003 , H03K19/007
CPC分类号： H03K19/00338
摘要： A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the resistive element to increase the latching speed of the hardened NCL circuit. Additionally, replacing transistors in an input driver, the feedback loop, and an inverter with transistor stacks, which may include two or more transistors connected in series, may harden the NCL circuit. Further, two NCL gates may be cross-coupled to harden the NCL circuit.
摘要翻译：提出了一种针对单事件颠簸（SEU）来硬化Null公约逻辑（NCL）电路的系统和方法。将电阻元件放置在NCL电路的反馈回路中可能使NCL电路硬化。旁路元件可以与电阻元件并联放置，以增加硬化NCL电路的锁定速度。此外，替代输入驱动器，反馈回路中的晶体管以及可包括串联连接的两个或更多个晶体管的晶体管堆叠的反相器可以使NCL电路硬化。此外，两个NCL门可以交叉耦合以硬化NCL电路。

6. 发明授权

US06396305B1 Digital leakage compensation circuit 有权
标题翻译：数字泄漏补偿电路
公开(公告)号：US06396305B1
公开(公告)日：2002-05-28
申请号：US09823191
申请日：2001-03-29
申请人： Roy M. Carlson
发明人： Roy M. Carlson
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A digital leakage compensation circuit for compensating for leakage in a dynamic circuit includes a dummy precharge circuit, a dummy input circuit, a dummy evaluation circuit, a dummy latching circuit, a sense circuit and a storage circuit. The dummy circuitry matches the size and layout of corresponding precharge, input, evaluation and latching circuitry in the dynamic circuit so that the leakage can be accurately modeled. The sense circuit senses the leakage and generates a signal, stored in the storage circuit, which causes an adjustable latching circuit to provide additional leakage compensation in the dynamic circuit. Alternatively, the dynamic circuit may include a driving circuit with an adjustable trip point. The sense circuit provides the signal to the driving circuit to adjust the trip point to compensate for the leakage.
摘要翻译：用于补偿动态电路中的泄漏的数字泄漏补偿电路包括虚拟预充电电路，虚拟输入电路，虚拟评估电路，虚拟锁存电路，感测电路和存储电路。虚拟电路匹配动态电路中对应的预充电，输入，评估和锁存电路的尺寸和布局，从而可以精确地建模泄漏。感测电路感测泄漏并产生存储在存储电路中的信号，这导致可调节的锁存电路在动态电路中提供附加的泄漏补偿。或者，动态电路可以包括具有可调节跳变点的驱动电路。感测电路向驱动电路提供信号以调整跳闸点以补偿泄漏。

7. 发明申请

US20080115023A1 SET HARDENED REGISTER 审中-公开
标题翻译：设置硬化寄存器
公开(公告)号：US20080115023A1
公开(公告)日：2008-05-15
申请号：US11553786
申请日：2006-10-27
申请人： Roy M. Carlson
发明人： Roy M. Carlson
IPC分类号： G01R31/28
CPC分类号： H03K19/0033 , G11C11/4125 , H03K5/1252 , H03K19/00338
摘要： A radiation hardened latch and a method of operation. To mitigate SET effects, the latch includes an internally located pulse rejection inverter. The pulse rejection inverter receives an input logic signal, delays it, and compares the delay logic signal to the input logic signal. If the input logic signal and the delayed logic signal are equivalent, the delayed logic signal is allowed to propagate through the pulse rejection inverter. Because the pulse rejection inverter is internally located, SET events that occur upstream or internal to the latch or on clock signaling are mitigated.
摘要翻译：辐射硬化闩锁和操作方法。为了减轻SET效应，锁存器包括一个内部定位的脉冲抑制逆变器。脉冲抑制逆变器接收输入逻辑信号，将其延迟，并将延迟逻辑信号与输入逻辑信号进行比较。如果输入逻辑信号和延迟逻辑信号是等效的，则允许延迟的逻辑信号通过脉冲抑制反相器传播。因为脉冲抑制逆变器在内部，所以在锁存器或时钟信号上游或内部发生的SET事件得到缓解。

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