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1. 发明授权

US07679403B2 Dual redundant dynamic logic 失效
标题翻译：双冗余动态逻辑
公开(公告)号：US07679403B2
公开(公告)日：2010-03-16
申请号：US11269212
申请日：2005-11-08
申请人： David O. Erstad
发明人： David O. Erstad
IPC分类号： H03K19/096
CPC分类号： H03K19/00338 , G11C11/4125 , H03K19/0075 , H03K19/0963
摘要： A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.
摘要翻译：描述了针对单事件不正常来强化动态逻辑的系统和方法。预充电电路被硬化，然后连接到两个下拉网络。两个下拉网络是冗余的，并且在正常操作条件下，当接收基本相同的输入时，提供基本相同的输出。然后，这两个输出被投票以提供针对单个事件不安的硬化输出。或者，两个输出可以连接到下一级的动态逻辑电路或用于评估的其它电路。

2. 发明授权

US07619455B2 Digital single event transient hardened register using adaptive hold 有权
标题翻译：数字单事件瞬态硬化寄存器采用自适应保持
公开(公告)号：US07619455B2
公开(公告)日：2009-11-17
申请号：US11737225
申请日：2007-04-19
申请人： Roy M. Carlson , David O. Erstad
发明人： Roy M. Carlson , David O. Erstad
IPC分类号： H03K3/356
CPC分类号： H03K19/007 , G11C5/005 , H03K3/0375 , H03K3/3562 , H03K5/1534 , H03K5/19
摘要： By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.
摘要翻译：通过调整寄存器的捕获时钟边沿定时，使得当数据返回到正确状态时，寄存器捕获数据，寄存器可能受到保护，防止DSET发生故障。如果在时钟沿附近发生数据毛刺，则寄存器输出的有效时间增加（CLK至Q）。当在时钟边缘附近检测到DSET瞬态的存在时，会出现这种有效的时间增加。

3. 发明授权

US08399845B2 Neutron detector cell efficiency 有权
标题翻译：中子检测器电池效率
公开(公告)号：US08399845B2
公开(公告)日：2013-03-19
申请号：US13424269
申请日：2012-03-19
申请人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
发明人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
IPC分类号： G01T3/00
CPC分类号： G01T3/08 , G11C5/005
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译：阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。

4. 发明授权

US06794908B2 Radiation-hard circuit 有权
标题翻译：辐射硬电路
公开(公告)号：US06794908B2
公开(公告)日：2004-09-21
申请号：US10452557
申请日：2003-05-30
申请人： David O. Erstad
发明人： David O. Erstad
IPC分类号： H03B100
CPC分类号： H01L27/1203 , H01L29/78615 , H03K19/00338
摘要： A radiation hardening circuit that includes two series-connected transistors that can replace any single transistor in a circuit. The hardening circuit includes a resistor that has a first node and a second node, a first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal. The first node of the resistor may be conductively connected to the drain terminal of the first transistor and the second node of the resistor is conductively connected to the body terminal of the first transistor. The hardening circuit also includes a second transistor in series with the first transistor, driven so that both transistors are off or on at any given time. The circuit is resistant to radiation-induced events due to the body bias of the first transistor, the off state of the second transistor, and the current limiting effect of the resistor.
摘要翻译：一种辐射硬化电路，包括两个串联连接的晶体管，可以替代电路中的任何一个晶体管。硬化电路包括具有第一节点和第二节点的电阻器，具有源极端子，栅极端子，漏极端子和主体端子的第一晶体管。电阻器的第一节点可以导电地连接到第一晶体管的漏极端子，并且电阻器的第二节点导电地连接到第一晶体管的主体端子。硬化电路还包括与第一晶体管串联的第二晶体管，被驱动以使得两个晶体管在任何给定时间断开或导通。该电路由于第一晶体管的体偏置，第二晶体管的截止状态和电阻器的限流效应而抵抗辐射诱发事件。

5. 发明授权

US07451384B2 Error recovery in asynchronous combinational logic circuits 失效
标题翻译：异步组合逻辑电路中的错误恢复
公开(公告)号：US07451384B2
公开(公告)日：2008-11-11
申请号：US10891654
申请日：2004-07-15
申请人： David O. Erstad , Roy M. Carlson
发明人： David O. Erstad , Roy M. Carlson
IPC分类号： G06F11/08
CPC分类号： H03K19/23 , H03K19/00392
摘要： A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.
摘要翻译：提出了一种向异步逻辑电路提供错误恢复的系统和方法。具有错误恢复的异步逻辑电路可以使用时间冗余来比较异步计算的结果并且如果需要的话启动错误恢复。使用多个异步寄存器选择器来比较异步逻辑电路的输出。如果异步寄存器选择器检测到不一致的结果，则异步寄存器选择器将自动清除。来自多个异步寄存器选择器的大多数公共数据输出被提供为表示异步逻辑电路的输出的输出。

6. 发明授权

US07804354B2 Circuit architecture for radiation resilience 有权
标题翻译：辐射弹性的电路架构
公开(公告)号：US07804354B2
公开(公告)日：2010-09-28
申请号：US11923017
申请日：2007-10-24
申请人： David O. Erstad
发明人： David O. Erstad
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/0033 , G11C29/02 , G11C29/021 , H01L2924/0002 , H03K19/0075 , H03K2017/0803 , H01L2924/00
摘要： A system and method for extending the operating life of a device susceptible to defects caused by total ionizing dose radiation and/or bias dependent degradation are described. The device is replicated at least once and at least one switching mechanism is used to cycle between the devices such that only one device is operating normally. While the first device is operating normally, the other devices are biased. The bias condition may slow, eliminate, or even reverse device shifts that occur due to total ionizing dose radiation or bias effects.
摘要翻译：描述了用于延长容易受到总电离剂量辐射和/或偏置依赖性降解引起的缺陷的装置的使用寿命的系统和方法。该设备至少复制一次，并且使用至少一个切换机构在设备之间循环，使得只有一个设备正常运行。当第一台设备运行正常时，其他设备有偏差。偏置条件可能会减慢，消除或甚至反转由于总电离剂量辐射或偏置效应而发生的器件偏移。

7. 发明授权

US07579879B2 Voting scheme for analog signals 失效
标题翻译：模拟信号投票方案
公开(公告)号：US07579879B2
公开(公告)日：2009-08-25
申请号：US11262081
申请日：2005-10-27
申请人： David O. Erstad , Bruce W. Ohme
发明人： David O. Erstad , Bruce W. Ohme
IPC分类号： G06F1/08
CPC分类号： H03K5/1252
摘要： A voting scheme for analog signals is described. An analog block is replicated to provide three analog blocks that are designed to have substantially the same analog output based on receiving substantially the same input. Voting is used to compare the analog outputs from the three analog blocks. In one example, the analog output from one of the three analog blocks having a middle value between the values of the other two analog outputs is provided as an output of the voter circuit. In another example, if the original analog block provides the analog output having the middle value, the output of the original analog block is provided as an output of the voter circuit. Otherwise, an output of another analog block is provided as an output of the voter circuit. In another example, the analog voter circuit determines which of the three analog outputs have been impacted by a transient event based on a non-zero output of transconductor circuits. These analog voting schemes may be incorporated into any circuit design in which an analog signal may be susceptible to SEE.
摘要翻译：描述模拟信号的投票方案。模拟块被复制以提供三个模拟块，其被设计为基于接收基本上相同的输入具有基本上相同的模拟输出。投票用于比较三个模拟块的模拟输出。在一个示例中，来自三个模拟块之一的模拟输出在其他两个模拟输出的值之间具有中间值，作为选举电路的输出。在另一示例中，如果原始模拟块提供具有中间值的模拟输出，则提供原始模拟块的输出作为选举电路的输出。否则，提供另一个模拟块的输出作为选举电路的输出。在另一示例中，模拟选择器电路确定三个模拟输出中的哪一个已经受到基于非导通电路的非零输出的瞬态事件的影响。这些模拟投票方案可以被并入到其中模拟信号可能易受SEE影响的任何电路设计中。

8. 发明授权

US06791362B1 System level hardening of asynchronous combinational logic 失效
标题翻译：异步组合逻辑的系统级硬化
公开(公告)号：US06791362B1
公开(公告)日：2004-09-14
申请号：US10731387
申请日：2003-12-09
申请人： Roy M. Carlson , David O. Erstad
发明人： Roy M. Carlson , David O. Erstad
IPC分类号： H03K1900
CPC分类号： G06F11/00
摘要： A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two asynchronous registers. A fault detector is used to detect a fault at an output of the asynchronous combinational logic circuit caused by SEU. If the fault detector detects a fault, a first asynchronous register is prevented from clearing stored data and a second asynchronous register is prevented from loading data from the asynchronous combinational logic circuit until the fault is cleared. Further, a timer circuit is used to ensure enough time elapses to allow the asynchronous combinational logic circuit to reevaluate itself. The asynchronous combinational logic circuit reevaluates itself by first propagating a NULL wave front to clear the fault and then propagating the data stored in the first asynchronous register to its outputs.
摘要翻译：提出了一种用于强化针对单事件颠簸（SEU）的异步组合逻辑电路的系统和方法。异步组合逻辑电路位于两个异步寄存器之间。故障检测器用于检测由SEU引起的异步组合逻辑电路的输出故障。如果故障检测器检测到故障，则防止第一异步寄存器清除存储的数据，并且防止第二异步寄存器从异步组合逻辑电路加载数据，直到故障被清除。此外，定时器电路用于确保足够的时间经过以允许异步组合逻辑电路重新评估其自身。异步组合逻辑电路通过首先传播NULL波前来清除故障，然后将存储在第一异步寄存器中的数据传播到其输出来重新评估自身。

9. 发明申请

US20120228513A1 NEUTRON DETECTOR CELL EFFICIENCY 有权
标题翻译：中子检测器细胞效率
公开(公告)号：US20120228513A1
公开(公告)日：2012-09-13
申请号：US13424269
申请日：2012-03-19
申请人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
发明人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
IPC分类号： G01T1/24
CPC分类号： G01T3/08 , G11C5/005
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译：阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。

10. 发明申请

US20090108912A1 Circuit Architecture for Radiation Resilience 有权
标题翻译：辐射韧性电路结构
公开(公告)号：US20090108912A1
公开(公告)日：2009-04-30
申请号：US11923017
申请日：2007-10-24
申请人： David O. Erstad
发明人： David O. Erstad
IPC分类号： G05F1/10
CPC分类号： H03K19/0033 , G11C29/02 , G11C29/021 , H01L2924/0002 , H03K19/0075 , H03K2017/0803 , H01L2924/00
摘要： A system and method for extending the operating life of a device susceptible to defects caused by total ionizing dose radiation and/or bias dependent degradation are described. The device is replicated at least once and at least one switching mechanism is used to cycle between the devices such that only one device is operating normally. While the first device is operating normally, the other devices are biased. The bias condition may slow, eliminate, or even reverse device shifts that occur due to total ionizing dose radiation or bias effects.
摘要翻译：描述了用于延长容易受到总电离剂量辐射和/或偏置依赖性降解引起的缺陷的装置的使用寿命的系统和方法。该设备至少复制一次，并且使用至少一个切换机构在设备之间循环，使得只有一个设备正常运行。当第一台设备运行正常时，其他设备有偏差。偏置条件可能会减慢，消除或甚至反转由于总电离剂量辐射或偏置效应而发生的器件偏移。

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