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1. 发明授权

US08809953B2 FET structures with trench implantation to improve back channel leakage and body resistance 有权
标题翻译：具有沟槽注入的FET结构，以改善背沟道泄漏和体电阻
公开(公告)号：US08809953B2
公开(公告)日：2014-08-19
申请号：US13426547
申请日：2012-03-21
申请人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.
摘要翻译：一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

2. 发明申请

US20120086077A1 FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE 有权
标题翻译：具有TRENCH植入的FET结构以提高反向通道泄漏和体电阻
公开(公告)号：US20120086077A1
公开(公告)日：2012-04-12
申请号：US12899635
申请日：2010-10-07
申请人： DAVID M FRIED , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： DAVID M FRIED , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.
摘要翻译：半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。在其他示例性实施例中，没有接合对接。在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

3. 发明授权

US08236632B2 FET structures with trench implantation to improve back channel leakage and body resistance 有权
标题翻译：具有沟槽注入的FET结构，以改善背沟道泄漏和体电阻
公开(公告)号：US08236632B2
公开(公告)日：2012-08-07
申请号：US12899635
申请日：2010-10-07
申请人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/338
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.
摘要翻译：半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。在其他示例性实施例中，没有接合对接。在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

4. 发明申请

US20120187490A1 FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE 有权
标题翻译：具有TRENCH植入的FET结构以提高反向通道泄漏和体电阻
公开(公告)号：US20120187490A1
公开(公告)日：2012-07-26
申请号：US13426547
申请日：2012-03-21
申请人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.
摘要翻译：一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

5. 发明授权

US09484269B2 Structure and method to control bottom corner threshold in an SOI device 有权
标题翻译：在SOI器件中控制底角阈值的结构和方法
公开(公告)号：US09484269B2
公开(公告)日：2016-11-01
申请号：US12822492
申请日：2010-06-24
申请人： Joseph Ervin , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Joseph Ervin , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L27/12 , H01L21/8242 , H01L21/84 , H01L21/762 , H01L27/108
CPC分类号： H01L21/84 , H01L21/76237 , H01L27/10847 , H01L27/1203
摘要： Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.
摘要翻译：半导体结构和方法来控制绝缘体上硅（SOI）器件中的底角阈值。一种方法包括掺杂绝缘体上半导体（SOI）岛的角区域。掺杂包括定制角区域的局部掺杂以减少SOI岛与相邻结构的电容耦合。

6. 发明授权

US08395217B1 Isolation in CMOSFET devices utilizing buried air bags 有权
标题翻译：使用埋入式气囊的CMOSFET器件中的隔离
公开(公告)号：US08395217B1
公开(公告)日：2013-03-12
申请号：US13283031
申请日：2011-10-27
申请人： Kangguo Cheng , Joseph Ervin , Jeffrey B. Johnson , Pranita Kulkarni , Kevin McStay , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Kangguo Cheng , Joseph Ervin , Jeffrey B. Johnson , Pranita Kulkarni , Kevin McStay , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L21/76289 , H01L21/823878 , H01L27/1203
摘要： A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.
摘要翻译：提供了具有隔离区域的半导体器件结构及其制造方法。半导体器件结构包括绝缘体上硅（SOI）衬底。在SOI衬底上形成多个栅极。半导体器件结构还包括形成在多个栅极中的每一个之间的具有侧壁的沟槽。半导体器件结构还包括形成在沟槽中的外延横向生长层。外延横向生长层从沟槽的相对侧壁横向生长，使得外延横向生长层包围延伸到SOI衬底中的沟槽的一部分。外延横向生长层以这样的方式形成，使得其包括覆盖SOI衬底的掩埋介电层的气隙区域。

7. 发明授权

US08835994B2 Reduced corner leakage in SOI structure and method 有权
公开(公告)号：US08835994B2
公开(公告)日：2014-09-16
申请号：US12791372
申请日：2010-06-01
申请人： Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L29/76 , H01L29/94 , H01L29/786 , H01L27/12 , H01L21/84 , H01L29/66 , H01L27/108 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/1087 , H01L27/10873 , H01L27/1203 , H01L29/66181 , H01L29/78603 , H01L29/78609 , H01L29/78696 , H01L29/945
摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

8. 发明申请

US20110291169A1 REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD 有权
标题翻译： SOI结构和方法中减少的角膜泄漏
公开(公告)号：US20110291169A1
公开(公告)日：2011-12-01
申请号：US12791372
申请日：2010-06-01
申请人： Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L27/12 , H01L21/86 , H01L29/78
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/1087 , H01L27/10873 , H01L27/1203 , H01L29/66181 , H01L29/78603 , H01L29/78609 , H01L29/78696 , H01L29/945
摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.
摘要翻译：通过在沟槽中提供衬垫，切割有源半导体层中的导电沟道区域，蚀刻导电沟道的侧面，拐角和/或底部，其中底切暴露半导体材料来提供用于减少晶体管泄漏的复古掺杂的结构替代方案在有源层中，用绝缘体代替导电沟道的去除部分。传导通道的这种整形增加了相邻电路元件的距离，如果充电，电荷可能会导致电压并导致导通通道区域中的反向通道阈值的变化并且减小了通道的横截面积通道的传导不能很好地控制; 这两种效应显着降低了晶体管的泄漏。

9. 发明授权

US09076817B2 Epitaxial extension CMOS transistor 有权
标题翻译：外延扩展CMOS晶体管
公开(公告)号：US09076817B2
公开(公告)日：2015-07-07
申请号：US13198152
申请日：2011-08-04
申请人： Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L29/66 , H01L29/51
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
摘要翻译：通过在半导体层上形成围绕栅极结构的第一深度的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔物，以覆盖第一并且通过形成大于第一深度的第二深度的一对第二沟槽。去除一次性间隔物，并进行选择性外延以形成集成的外延源和源极延伸区域以及集成的外延漏极和漏极延伸区域。可以在平坦化介电层的沉积和平坦化之后形成替代栅极结构，并且随后去除栅极结构并且在外延源极和漏极延伸区域上横向扩展栅极腔。或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

10. 发明申请

US20130134491A1 POLYSILICON/METAL CONTACT RESISTANCE IN DEEP TRENCH 有权
标题翻译：深层TRENCH中的多晶硅/金属接触电阻
公开(公告)号：US20130134491A1
公开(公告)日：2013-05-30
申请号：US13307874
申请日：2011-11-30
申请人： Brian W. Messenger , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Brian W. Messenger , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L27/10829 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.
摘要翻译：一种形成沟槽结构的方法，其包括在至少沟槽的侧壁上形成含金属层，以及在所述沟槽内形成未掺杂的半导体填充材料。未掺杂的半导体填充材料和含金属层通过第一蚀刻凹陷到沟槽内的第一深度。然后将未掺杂的半导体填充材料凹入到沟槽内的第二深度，其大于具有第二蚀刻的第一深度。第二蚀刻暴露了含金属层的至少一个侧壁部分。沟槽填充有掺杂的半导体含有材料填充物，其中掺杂半导体材料填充物与含金属层的至少侧壁部分直接接触。

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