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1. 发明申请

US20070019790A1 Radiation sensitive film including a measuring scale 有权
标题翻译：辐射敏感膜包括测量刻度
公开(公告)号：US20070019790A1
公开(公告)日：2007-01-25
申请号：US11282095
申请日：2005-11-17
申请人： David Lewis , Carl Listl , Xiang Yu
发明人： David Lewis , Carl Listl , Xiang Yu
IPC分类号： H05G1/28
CPC分类号： G03F7/025 , A61B5/1075 , A61N5/1048
摘要： An article of manufacture comprising a radiation sensitive material, and a measuring scale that is part of the radiation sensitive material. A method of measuring at least one parameter relating to an irradiated material is also described. A radiation sensitive material including a measuring scale is exposed to radiation and at least one parameter relating to one or more exposed areas of the material is measured by reference to the measuring scale on the material.
摘要翻译：包括辐射敏感材料的制品和作为辐射敏感材料的一部分的测量刻度。还描述了测量与被照射材料有关的至少一个参数的方法。包括测量刻度的辐射敏感材料暴露于辐射，并且通过参考材料上的测量刻度来测量与材料的一个或多个暴露区域有关的至少一个参数。

2. 发明申请

US20060134551A1 Lithium salt of polyacetylene as radiation sensitive filaments and preparation and use thereof 有权
标题翻译：聚乙炔锂盐作为辐射敏感丝及其制备和应用
公开(公告)号：US20060134551A1
公开(公告)日：2006-06-22
申请号：US11338017
申请日：2006-01-24
申请人： Janette Anyumba , David Lewis , Hsiao-Yi Shih , Xiang Yu
发明人： Janette Anyumba , David Lewis , Hsiao-Yi Shih , Xiang Yu
IPC分类号： G03C1/76
CPC分类号： G03F7/025 , G03C1/733 , G03F7/029
摘要： This invention relates to photochromic filaments composed of the lithium salt of a conjugated, polymerizable polyacetylene having a carboxylic acid or carboxylate terminal group wherein the length to width ratio of said filaments is between about 5000:1 and about 5:1 and the average length of the filament is up to about 5 cm. The invention also pertains to the use of said salts in maximized radiation sensitivity for imaging, radiation dose measurement or mapping and detection of radiation fields.
摘要翻译：本发明涉及由具有羧酸或羧酸酯端基的共轭可聚合聚乙炔的锂盐组成的光致变色长丝，其中所述长丝的长宽比为约5000:1至约5:1，平均长度为灯丝长达约5厘米。本发明还涉及使用所述盐以最大的辐射敏感度进行成像，辐射剂量测量或辐射场的映射和检测。

3. 发明授权

US09697309B1 Metastability-hardened synchronization circuit 有权
公开(公告)号：US09697309B1
公开(公告)日：2017-07-04
申请号：US12563095
申请日：2009-09-18
申请人： Ryan Fung , David Lewis , David Neto
发明人： Ryan Fung , David Lewis , David Neto
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F17/5054 , H03K3/0375
摘要： An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

4. 发明授权

US08984367B2 Error detection and correction circuitry 有权
标题翻译：错误检测和校正电路
公开(公告)号：US08984367B2
公开(公告)日：2015-03-17
申请号：US13035826
申请日：2011-02-25
申请人： Paul B. Ekas , David Lewis
发明人： Paul B. Ekas , David Lewis
IPC分类号： G11C29/00 , G11C29/52 , G06F11/10 , H03K19/177 , G11C11/412 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/10 , G06F11/1048 , G11C11/412 , G11C29/52 , G11C2029/0411 , H03K19/17768
摘要： Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.
摘要翻译：具有存储器电路的集成电路可以包括错误检测电路和纠错电路。误差检测电路可用于检测存储器电路中的软错误。错误检测电路可以包括用于执行奇偶校验的逻辑门。错误检测电路可以具有交织结构以提供交错数据位处理，可以具有减少逻辑门延迟的树结构，并且可以被流水线化以优化性能。存储器电路可以与交错结构一起加载交错奇偶校验位以提供多位错误检测能力。奇偶校验位可以使用设计工具预先计算或在设备配置期间计算。响应于存储器错误的检测，错误校正电路可用于扫描存储器电路的期望部分并校正存储器错误。

5. 发明授权

US08804295B2 Configurable multi-gate switch circuitry 有权
标题翻译：可配置的多门开关电路
公开(公告)号：US08804295B2
公开(公告)日：2014-08-12
申请号：US12579792
申请日：2009-10-15
申请人： David Lewis
发明人： David Lewis
IPC分类号： H01H47/26 , H01H50/12 , H01H57/00 , H01L29/788
CPC分类号： H01H45/14 , H01H59/00 , H01H59/0009
摘要： Integrated circuits with configurable multi-gate switch circuitry are provided. The switch circuitry may include switch control circuitry and an array of multi-gate switches. Each multi-gate switch may have first and second terminals, first and second gates, and a metal bridge. The metal bridge is attached to the first terminal. The metal bridge may extend over the gates and may hover above the second terminal in the off state. The metal bridge may have a tip that bends down to physically contact the second terminal in the on state. Switch control circuitry may provide row and column control signals to load desired switch states into the switch array. The switch array may be partitioned into groups of switches that form multiplexers. The multiplexers may be used in programmable circuits such as programmable logic device circuits.
摘要翻译：提供了具有可配置的多栅极开关电路的集成电路。开关电路可以包括开关控制电路和多栅极开关阵列。每个多栅极开关可以具有第一和第二端子，第一和第二栅极以及金属桥。金属桥连接到第一个终端。金属桥可以在门上延伸，并且可以在关闭状态下悬停在第二端子上方。金属桥可以具有向下弯曲的尖端，以在接通状态下物理地接触第二端子。开关控制电路可以提供行和列控制信号以将期望的开关状态加载到开关阵列中。开关阵列可以被划分为形成多路复用器的开关组。多路复用器可以用于诸如可编程逻辑器件电路的可编程电路中。

6. 发明授权

US08753696B1 Methods for preparing cannabis and related products 失效
标题翻译：制备大麻及相关产品的方法
公开(公告)号：US08753696B1
公开(公告)日：2014-06-17
申请号：US13652609
申请日：2012-10-16
申请人： David Lewis
发明人： David Lewis
IPC分类号： A01N65/00
CPC分类号： A61K36/185 , A61K9/007
摘要： A method for preparing a medical marijuana mixture includes combining prepared medical marijuana and an alkaline substance in a pulverizing device. The alkaline substance may be coconut, cinnamon, or the like. The pulverizing device may be a coffee grinder, a food processor, a blender, or the like. The mixture may optionally include a sweetener, such as sugar, stevia, or the like.
摘要翻译：制备医用大麻混合物的方法包括将制备的医用大麻和碱性物质混合在粉碎装置中。碱性物质可以是椰子，肉桂等。粉碎装置可以是咖啡研磨机，食品加工机，搅拌机等。混合物可以任选地包括甜味剂，例如糖，甜叶菊等。

7. 发明授权

US08550092B2 Filter 有权
标题翻译：过滤
公开(公告)号：US08550092B2
公开(公告)日：2013-10-08
申请号：US12669463
申请日：2008-06-27
申请人： John Roger Sampson , David Lewis
发明人： John Roger Sampson , David Lewis
IPC分类号： A24D3/04
CPC分类号： A24D3/10 , A24D3/0212 , A24D3/048 , A24D3/063
摘要： A filter for a cigarette comprises a porous filter rod (3) a material sheet (2) wrapped around the filter rod and a cellulose acetate thread (4) formed from substantially uncrimped cellulose acetate filaments. The cellulose acetate thread is positioned within the filter rod and extends along the central axis of the filter rod.
摘要翻译：用于香烟的过滤器包括多孔过滤棒（3）围绕过滤杆缠绕的材料片（2）和由基本上未卷曲的醋酸纤维素丝形成的醋酸纤维素丝线（4）。醋酸纤维线被定位在过滤杆内，并沿过滤杆的中心轴延伸。

8. 发明授权

US08537284B2 Adjacent channel power scan 有权
标题翻译：相邻通道功率扫描
公开(公告)号：US08537284B2
公开(公告)日：2013-09-17
申请号：US12408150
申请日：2009-03-20
申请人： Xiaoqiang Ma , Azzedine Touzni , Jason Adams , David Lewis , Louis Giannini , Feng Huang
发明人： Xiaoqiang Ma , Azzedine Touzni , Jason Adams , David Lewis , Louis Giannini , Feng Huang
IPC分类号： H04N5/00 , H04N5/63 , H04N5/44
CPC分类号： H04B1/1027 , H04B2001/1045 , H04N5/21 , H04N5/4401 , H04N21/4263 , H04N21/4382
摘要： A method and apparatus are disclosed for determining the presence of adjacent channel interference. Received digital signals are processed to detect the existence of strong channels adjacent to the channel of interest and control signals may be generated based on the detection of strong adjacent channels. The control signals are then used to adjust the signal power of the received signals.
摘要翻译：公开了一种用于确定相邻信道干扰的存在的方法和装置。处理接收到的数字信号以检测与感兴趣信道相邻的强信道的存在，并且可以基于强相邻信道的检测来生成控制信号。然后控制信号用于调整接收信号的信号功率。

9. 发明授权

US08525557B1 Merged tristate multiplexer 有权
标题翻译：合并三态多路复用器
公开(公告)号：US08525557B1
公开(公告)日：2013-09-03
申请号：US13289841
申请日：2011-11-04
申请人： David Lewis
发明人： David Lewis
IPC分类号： G06F1/08
CPC分类号： H03K19/1737 , H03K17/693
摘要： Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.
摘要翻译：公开了与三态多路复用器电路相关的各种方法和结构。一个实施例提供了一种选择电路，其中有选择地使能的输入电路通过输出使能电路耦合到输出电路，使得所选择的一个有选择地使能的输入电路可操作地提供用于充电和放电的电流用于充电和放电输出电路晶体管栅极。在本公开中更全面地描述了这个和其他详细的实施例。

10. 发明授权

US08519763B2 Integrated circuits with dual-edge clocking 有权
标题翻译：具有双边沿时钟的集成电路
公开(公告)号：US08519763B2
公开(公告)日：2013-08-27
申请号：US12814344
申请日：2010-06-11
申请人： Ajay K. Ravi , David Lewis
发明人： Ajay K. Ravi , David Lewis
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , G06F1/10 , H03K5/1565
摘要： Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.
摘要翻译：提供支持双边沿时钟的集成电路。集成电路可以包括产生方波时钟信号的锁相环。时钟信号可以通过输入输出引脚从片外设备提供。时钟信号可以通过时钟分配网络路由，以向本地时钟信号提供脉冲发生器，以在时钟沿上升沿和下降沿产生时钟脉冲。脉冲发生器可以产生由具有公共脉冲宽度的上升和下降时钟沿触发的时钟脉冲，以获得最佳性能。时钟网络引入的占空比失真可能被最小化以获得最佳性能。可以使用自适应占空比失真电路来控制时钟缓冲器的上拉/下拉驱动强度，使得本地时钟信号的高时钟相位大约为半个时钟周期。

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