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1. 发明授权

US06202097B1 Methods for performing diagnostic functions in a multiprocessor data processing system having a serial diagnostic bus 失效
标题翻译：在具有串行诊断总线的多处理器数据处理系统中执行诊断功能的方法
公开(公告)号：US06202097B1
公开(公告)日：2001-03-13
申请号：US08373052
申请日：1995-01-17
申请人： David James Foster , Armando Garcia , Robert Bernard Pearson
发明人： David James Foster , Armando Garcia , Robert Bernard Pearson
IPC分类号： G06F15173
CPC分类号： G06F11/2242 , G06F11/2294 , G06F11/2736
摘要： Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.
摘要翻译：在具有多个处理节点（P0-P3）的多处理器系统（10）中使用的装置和方法，每个处理节点包括本地数据处理器（22a，28a）。该装置包括到控制器（14）的接口（42），该接口包括用于存储从控制器接收的功能（诸如诊断功能）的寄存器（48）。接口还包括用于将诊断功能作为分组提供给比特串行通信总线（40）的输入端的电路（50）。通信总线穿过多个处理节点中的每一个并且具有在该接口处终止的输出终端。每个节点包括用于接收分组的寄存器（54），并响应于此所传送的信息，用于暂停本地数据处理器并用于控制本地数据处理器控制信号线，数据信号线和地址信号线的操作执行诊断功能，例如从指定位置读取数据或将数据写入指定位置。本地数据处理器也可能被重置，重新启动，从停止状态重新启动或中断。

2. 发明授权

US5327570A Multiprocessor system having local write cache within each data processor node 失效
标题翻译：在每个数据处理器节点内具有本地写缓存的多处理器系统
公开(公告)号：US5327570A
公开(公告)日：1994-07-05
申请号：US734432
申请日：1991-07-22
申请人： David J. Foster , Armando Garcia , Robert B. Pearson
发明人： David J. Foster , Armando Garcia , Robert B. Pearson
IPC分类号： G06F13/00 , G06F13/36 , G06F13/40 , G06F15/16 , G06F9/00
CPC分类号： G06F13/4018
摘要： A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.
摘要翻译：一种多处理器数据处理系统（10）及其操作方法，以便提供共享系统资源（24,26）的有效带宽利用率。该系统包括多个处理器节点，每个处理器节点包括数据处理器（22a，28a）。在将数据发送到第二总线（32）之前，方法的第一步是将由数据处理器写入的数据缓冲到第一总线（23a）。缓冲还包括由数据处理器与由数据处理器写入的数据相结合的字节使能（BE）信号。下一步骤通过将缓冲的数据发送到第二总线来执行主存储器（26）的写入操作; 响应于所存储的BE信号，还发送用于指示是否将存储器写入作为读取 - 修改 - 写入（RMW）类型的存储器操作来实现的控制信号; 以及将所存储的BE信号发送到第二总线。另一步骤将数据，RMW信号和BE信号从第二总线耦合到第三总线（24）以供主存储器接收。

3. 发明授权

US5280591A Centralized backplane bus arbiter for multiprocessor systems 失效
标题翻译：用于多处理器系统的集中式背板总线仲裁器
公开(公告)号：US5280591A
公开(公告)日：1994-01-18
申请号：US733563
申请日：1991-07-22
申请人： Armando Garcia , Curtis S. McDowell , Wielming Sieh
发明人： Armando Garcia , Curtis S. McDowell , Wielming Sieh
IPC分类号： G06F13/362 , G06F13/364
CPC分类号： G06F13/364
摘要： An Arbiter (36) is coupled to a multiprocessor system (10) Global Bus (24) having two separate main buses: an address bus (ABUS) and a data bus (DBUS). Bus agents coupled to the Global Bus request access to use the buses by asserting bus request lines to the Arbiter. The Arbiter is a dual level, round robin Arbiter that employs a fast, single-cycle arbitration technique. During each system clock cycle, the Arbiter considers the signals on the request input lines and generates corresponding grant output lines which dictate, for the next cycle, which bus agent is to receive access to the address bus and which bus agent is to receive access to the data bus.
摘要翻译：仲裁器（36）耦合到具有两个分离的主总线的地址总线（ABUS）和数据总线（DBUS）的多处理器系统（10）全局总线（24）。与全局总线相连的总线代理请求通过向仲裁器断言总线请求线来访问总线。仲裁者是一个双级循环仲裁器，采用快速，单循环仲裁技术。在每个系统时钟周期期间，仲裁器考虑请求输入线路上的信号，并产生相应的授权输出线，这些线路指示下一个周期中哪个总线代理程序将接收对地址总线的访问以及哪个总线代理程序将接收访问数据总线。

4. 发明授权

US5870572A Universal buffered interface for coupling multiple processors, memory units, and I/O interfaces to a common high-speed interconnect 失效
标题翻译：通用缓冲接口，用于将多个处理器，存储器单元和I / O接口耦合到公共高速互连
公开(公告)号：US5870572A
公开(公告)日：1999-02-09
申请号：US798186
申请日：1996-12-23
申请人： Armando Garcia
发明人： Armando Garcia
IPC分类号： G06F13/24 , G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/17
CPC分类号： G06F13/4217 , G06F13/24 , G06F13/387 , G06F13/4036
摘要： A multiprocessor data processing system includes a group of computational data processor nodes including at least one communication data processor node, at least one shared global memory with memory banks, and a number of bus interfaces each coupled between one of a set of local buses and a global bus. Each interface includes a number of input queues and output queues coupled between the local bus and the global bus. The interface supports the use of an inter-processor communication (IPC) mechanism that allows any processor to send an interrupt to any other processor in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, with the interrupt mask identifying the processor or processors to be interrupted for interprocessor communication.
摘要翻译：多处理器数据处理系统包括一组计算数据处理器节点，包括至少一个通信数据处理器节点，至少一个具有存储体的共享全局存储器以及多个总线接口，每个总线接口分别耦合在一组局部总线和全球巴士每个接口包括耦合在本地总线和全局总线之间的多个输入队列和输出队列。该接口支持使用处理器间通信（IPC）机制，允许任何处理器在单个全局总线周期期间向系统中的任何其他处理器发送中断。在特别标记的总线周期期间，中断屏蔽将通过地址总线进行传输，中断屏蔽标识要处理器或处理器中断处理器间通信。

5. 发明授权

US5469542A Serial diagnostic interface bus for multiprocessor systems 失效
标题翻译：用于多处理器系统的串行诊断接口总线
公开(公告)号：US5469542A
公开(公告)日：1995-11-21
申请号：US733767
申请日：1991-07-22
申请人： David J. Foster , Armando Garcia , Robert B. Pearson
发明人： David J. Foster , Armando Garcia , Robert B. Pearson
IPC分类号： G06F15/16 , G06F11/27 , G06F11/273 , G06F15/177 , G06F13/00 , G06F11/00
CPC分类号： G06F11/2242 , G06F11/2294 , G06F11/2736
摘要： Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.
摘要翻译：在具有多个处理节点（P0-P3）的多处理器系统（10）中使用的装置和方法，每个处理节点包括本地数据处理器（22a，28a）。该装置包括到控制器（14）的接口（42），该接口包括用于存储从控制器接收的功能（诸如诊断功能）的寄存器（48）。接口还包括用于将诊断功能作为分组提供给比特串行通信总线（40）的输入端的电路（50）。通信总线穿过多个处理节点中的每一个并且具有在该接口处终止的输出终端。每个节点包括用于接收分组的寄存器（54），并响应于此所传送的信息，用于暂停本地数据处理器并用于控制本地数据处理器控制信号线，数据信号线和地址信号线的操作执行诊断功能，例如从指定位置读取数据或将数据写入指定位置。本地数据处理器也可能被重置，重新启动，从停止状态重新启动或中断。

6. 发明授权

US5410654A Interface with address decoder for selectively generating first and second address and control signals respectively in response to received address and control signals 失效
标题翻译：与地址解码器的接口，用于响应于接收的地址和控制信号分别选择性地产生第一和第二地址和控制信号
公开(公告)号：US5410654A
公开(公告)日：1995-04-25
申请号：US733517
申请日：1991-07-22
申请人： David J. Foster , Armando Garcia
发明人： David J. Foster , Armando Garcia
IPC分类号： G06F12/08 , G06F13/42 , G06F15/17 , G06F15/02
CPC分类号： G06F13/4217 , G06F12/0835 , G06F15/17
摘要： Interface circuitry for coupling to a microprocessor device. The interface circuitry includes an input for receiving address signal lines and control signal lines generated by the microprocessor device. The interface further includes an address decoder, responsive to the received address signal lines, for determining if a microprocessor-generated memory access is directed to a private memory, accessible only by the microprocessor device, or to a shared memory that is accessible by a plurality of microprocessor devices. Responsive to the address decoder, the interface circuitry provides first address signal lines and first control signal lines to the private memory in response to the microprocessor device generating a memory access to the private memory. Also responsive to the address decoder, the interface circuitry provides second address signal lines and second control signal lines for coupling to the shared memory in response to the microprocessor device generating a memory access to the shared memory. The interface circuitry further includes interrupt control circuitry, inter-processor interrupt circuitry, DMA circuitry, a serial bus interface, and also provides a plurality of miscellaneous functions for the microprocessor.
摘要翻译：用于耦合到微处理器设备的接口电路。接口电路包括用于接收由微处理器设备产生的地址信号线和控制信号线的输入。接口还包括响应于所接收的地址信号线的地址解码器，用于确定微处理器产生的存储器访问是否被引导到仅可由微处理器设备访问的专用存储器，或者可由多个可访问的共享存储器的微处理器设备。响应于地址解码器，接口电路响应于微处理器设备产生对专用存储器的存储器访问，向专用存储器提供第一地址信号线和第一控制信号线。还响应于地址解码器，接口电路提供第二地址信号线和第二控制信号线，以响应于微处理器设备产生对共享存储器的存储器访问而耦合到共享存储器。接口电路还包括中断控制电路，处理器间中断电路，DMA电路，串行总线接口，并且还为微处理器提供多种其他功能。

7. 发明授权

US5588122A Universal buffered interface for coupling multiple processors memory units, and I/O interfaces to a common high-speed interconnect 失效
标题翻译：通用缓冲接口，用于耦合多个处理器内存单元，以及I / O接口连接到一个通用的高速互连
公开(公告)号：US5588122A
公开(公告)日：1996-12-24
申请号：US260107
申请日：1994-06-15
申请人： Armando Garcia
发明人： Armando Garcia
IPC分类号： G06F13/24 , G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/17
CPC分类号： G06F13/4217 , G06F13/24 , G06F13/387 , G06F13/4036
摘要： A universal buffered interface (UBIF 34) couples a local bus (32) to a global bus (24) and supports, on the local bus, up to four nodes. The nodes may be comprised of processors (22a, 28a), memory banks, and/or I/O interfaces. Each processor has an associated private memory. The UBIF includes bidirectional, first-in-first-out (FIFO) buffers, or queues, for each node and operates in conjunction with a two-level bus hierarchy. The UBIF supports decoupled global memory (26) read requests and replies, supports decoupled, atomic read-modify-write operations to Global Memory, and block-read support for transferring contiguous blocks of global memory to processors or I/O interfaces. The UBIF also enables the use of an inter-processor communication (IPC) mechanism that enables any processor to send an interrupt to any other processor or processors in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, the interrupt mask identifying the processor or processors to be interrupted.
摘要翻译：通用缓冲接口（UBIF 34）将本地总线（32）耦合到全局总线（24），并且在本地总线上支持多达四个节点。节点可以由处理器（22a，28a），存储器组和/或I / O接口组成。每个处理器都有一个关联的私有内存。 UBIF包括针对每个节点的双向，先进先出（FIFO）缓冲区或队列，并与两级总线层次结构一起运行。 UBIF支持解耦全局内存（26）读取请求和答复，支持对全局内存进行解耦，原子读取 - 修改 - 写入操作，以及块读取支持，将全局内存的连续块传输到处理器或I / O接口。 UBIF还能够使用处理器间通信（IPC）机制，使机构能够在单个全局总线周期内使任何处理器向系统中的任何其他处理器或处理器发送中断。在特别标记的总线周期中，中断屏蔽通过地址总线传输，中断屏蔽识别要中断的处理器或处理器。

8. 发明授权

US5463755A High-performance, multi-bank global memory card for multiprocessor systems 失效
标题翻译：用于多处理器系统的高性能，多存储全球存储卡
公开(公告)号：US5463755A
公开(公告)日：1995-10-31
申请号：US263746
申请日：1994-06-22
申请人： Daniel P. Dumarot , Armando Garcia
发明人： Daniel P. Dumarot , Armando Garcia
IPC分类号： G06F12/06 , G06F13/16 , G06F15/16 , G06F15/177 , G06F11/10 , G06F12/14
CPC分类号： G06F13/1663 , G06F12/0607 , G06F13/1647
摘要： A multi-bank global memory system (GMS) for use with a multiprocessor computer system having a global bus. The GMS includes up to four global memory cards (GMCs) connected to the global bus. The GMCs are independently accessed. Each of the GMCs includes a common interface for buffering memory accesses and read reply data. Each of the GMCs also includes four memory banks. The common interface and memory banks are connected via a local bus. The memory banks are interleaved and are independently scheduled and accessed. The common interface and memory banks are each capable of performing posted write cycles and independently supplying read reply data subsequent to read requests. The common interface is capable of buffering, simultaneously, up to 8 writes per bank and 8 read replies per bank.
摘要翻译：一种用于与具有全局总线的多处理器计算机系统一起使用的多存储体全局存储器系统（GMS）。 GMS包括连接到全局总线的最多四个全局存储卡（GMC）。 GMC是独立访问的。每个GMC包括用于缓冲存储器访问和读取应答数据的通用接口。每个GMC还包括四个存储体。公共接口和存储体通过本地总线连接。存储体被交织并被独立地调度和访问。公共接口和存储体各自能够执行发布的写周期，并且在读请求之后独立地提供读回应数据。通用接口能够同时缓存每个银行多达8个写入，每个银行8个读取回复。

9. 发明授权

US4694605A Mosquito eliminator 失效
标题翻译：灭蚊器
公开(公告)号：US4694605A
公开(公告)日：1987-09-22
申请号：US891373
申请日：1986-07-31
申请人： Armando Garcia , David V. Nesmith
发明人： Armando Garcia , David V. Nesmith
IPC分类号： A01M3/02
CPC分类号： A01M3/02
摘要： A switch device for swatting insects or for use as a brush and the like has a tubular handle, a switch in the handle formed from nylon strands which are folded double about a fold line, a cord having one end tied around the fold line to secure the switch and another end secured to the inner end of the handle. The switch can be fully retracted into the handle for storage or it can be pulled from the handle by different amounts to suit its different modes of use. The switch is retained in the handle by friction.
摘要翻译：用于打扫昆虫或用作刷子等的开关装置具有管状手柄，手柄中的开关由尼龙股线形成，折叠线折叠在一起，绳索的一端绑在折线上以固定开关和另一端固定到手柄的内端。开关可以完全缩回到手柄中进行存储，或者可以通过不同的量将其从手柄拉出以适应其不同的使用模式。开关通过摩擦保持在手柄中。

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