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1. 发明授权

US5327570A Multiprocessor system having local write cache within each data processor node 失效
标题翻译：在每个数据处理器节点内具有本地写缓存的多处理器系统
公开(公告)号：US5327570A
公开(公告)日：1994-07-05
申请号：US734432
申请日：1991-07-22
申请人： David J. Foster , Armando Garcia , Robert B. Pearson
发明人： David J. Foster , Armando Garcia , Robert B. Pearson
IPC分类号： G06F13/00 , G06F13/36 , G06F13/40 , G06F15/16 , G06F9/00
CPC分类号： G06F13/4018
摘要： A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.
摘要翻译：一种多处理器数据处理系统（10）及其操作方法，以便提供共享系统资源（24,26）的有效带宽利用率。该系统包括多个处理器节点，每个处理器节点包括数据处理器（22a，28a）。在将数据发送到第二总线（32）之前，方法的第一步是将由数据处理器写入的数据缓冲到第一总线（23a）。缓冲还包括由数据处理器与由数据处理器写入的数据相结合的字节使能（BE）信号。下一步骤通过将缓冲的数据发送到第二总线来执行主存储器（26）的写入操作; 响应于所存储的BE信号，还发送用于指示是否将存储器写入作为读取 - 修改 - 写入（RMW）类型的存储器操作来实现的控制信号; 以及将所存储的BE信号发送到第二总线。另一步骤将数据，RMW信号和BE信号从第二总线耦合到第三总线（24）以供主存储器接收。

2. 发明授权

US5469542A Serial diagnostic interface bus for multiprocessor systems 失效
标题翻译：用于多处理器系统的串行诊断接口总线
公开(公告)号：US5469542A
公开(公告)日：1995-11-21
申请号：US733767
申请日：1991-07-22
申请人： David J. Foster , Armando Garcia , Robert B. Pearson
发明人： David J. Foster , Armando Garcia , Robert B. Pearson
IPC分类号： G06F15/16 , G06F11/27 , G06F11/273 , G06F15/177 , G06F13/00 , G06F11/00
CPC分类号： G06F11/2242 , G06F11/2294 , G06F11/2736
摘要： Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.
摘要翻译：在具有多个处理节点（P0-P3）的多处理器系统（10）中使用的装置和方法，每个处理节点包括本地数据处理器（22a，28a）。该装置包括到控制器（14）的接口（42），该接口包括用于存储从控制器接收的功能（诸如诊断功能）的寄存器（48）。接口还包括用于将诊断功能作为分组提供给比特串行通信总线（40）的输入端的电路（50）。通信总线穿过多个处理节点中的每一个并且具有在该接口处终止的输出终端。每个节点包括用于接收分组的寄存器（54），并响应于此所传送的信息，用于暂停本地数据处理器并用于控制本地数据处理器控制信号线，数据信号线和地址信号线的操作执行诊断功能，例如从指定位置读取数据或将数据写入指定位置。本地数据处理器也可能被重置，重新启动，从停止状态重新启动或中断。

3. 发明授权

US4837678A Instruction sequencer for parallel operation of functional units 失效
标题翻译：用于并行运行功能单元的指令定序器
公开(公告)号：US4837678A
公开(公告)日：1989-06-06
申请号：US35349
申请日：1987-04-07
申请人： Glen J. Culler , Robert B. Pearson , Michael McCammon , William L. Proctor , John L. Richardson
发明人： Glen J. Culler , Robert B. Pearson , Michael McCammon , William L. Proctor , John L. Richardson
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/223 , G06F9/28 , G06F9/3802 , G06F9/3889
摘要： An instruction sequencer for programming parallel operations of functional units in response to an instruction stream is shown. The instruction sequencer includes a random access memory for storing instruction segments which program the operations of the functional units. An instruction address register contains instruction addresses for selected locations in the memory having instruction segments stored therein. A memory address circuit reads out an instruction stream comprising instruction segments from the memory in response to the stored instruction address and stores the same in an instruction buffer register. A rotating network, which is operatively coupled to the instruction buffer register, rotates the instruction stream so as to position a selected instruction segment at a predetermined location in a rotating network. A control circuit determines whether the rotating network is required to rotate the instruction stream and, if so, directs the rotating network to position the selected instruction segment at the predetermined location in the rotating network. A first decoding circuit receives and decodes the selected instruction segment to produce a first control signal. A shifting circuit receives the rotated instruction stream and shifts the same an amount equal to at least the width of the selected instruction segment and then applies the same to a second decoding circuit which produces a second control signal. The first and second control signals are adapted to be applied to and commence operation of the functional units in parallel.
摘要翻译：示出了用于响应于指令流来编程功能单元的并行操作的指令定序器。指令定序器包括用于存储对功能单元的操作进行编程的指令段的随机存取存储器。指令地址寄存器包含存储器中存储有指令段的选择位置的指令地址。存储器地址电路响应于存储的指令地址从存储器读出包括指令段的指令流，并将其存储在指令缓冲寄存器中。可操作地耦合到指令缓冲寄存器的旋转网络旋转指令流，以将所选择的指令段定位在旋转网络中的预定位置。控制电路确定旋转网络是否需要旋转指令流，如果是，则引导旋转网络将所选择的指令段定位在旋转网络中的预定位置。第一解码电路接收并解码所选择的指令段以产生第一控制信号。移位电路接收旋转的指令流，并移位相等于至少所选指令段的宽度的量，然后将其应用于产生第二控制信号的第二解码电路。第一和第二控制信号被并行地应用于并开始运行功能单元。

4. 发明授权

US5276684A High performance I/O processor 失效
标题翻译：高性能I / O处理器
公开(公告)号：US5276684A
公开(公告)日：1994-01-04
申请号：US734359
申请日：1991-07-22
申请人： Robert B. Pearson
发明人： Robert B. Pearson
IPC分类号： G06F13/00 , G06F13/12 , G06F13/28 , G06F13/38 , H04J3/24
CPC分类号： G06F13/28 , G06F13/124 , G06F13/128
摘要： An I/O Processor (28) includes a two channel receiver (28b) and a two channel transmitter (28c) coupled to a high speed communications channel. For the receiver a status memory, specifically a FIFO (44a, 44b), stores structuring information that indicates the beginnings (SOP) and endings (EOP) of PACKETS, as well as, for each BURST of data words within a packet, an indication of the occurrence of the BURST and a length (L) of the BURST. Additionally, there is an indication for each BURST of the presence of any errors occurring during the BURST. A corresponding data FIFO (40a, 40b) contains only the received data words, without any structuring information. A device reads both of the FIFOS, subsequent to the reception of one or more PACKETS, so as to reconstruct the original format of the received data. For the transmitter a structure control FIFO (46a, 46b) stores the structuring information for an associated data FIFO (40c, 40d) , the transmitted data being structured in accordance with the structuring information. The receiver and the transmitter each include a high speed internal data path (42a, 42b) and a lower speed data path (54a, 54b) which are coupled together during slave read and write cycles, and which are decoupled during high speed DMA cycles.
摘要翻译： I / O处理器（28）包括耦合到高速通信信道的双通道接收器（28b）和双通道发送器（28c）。对于接收机，状态存储器，特别是FIFO（44a，44b）存储指示PACKETS的开始（SOP）和结束（EOP）的结构化信息，以及对于分组内的数据字的每个BURST，指示 BURST的发生和BURST的长度（L）。此外，每个BURST有一个指示是否存在在BURST期间发生的任何错误。对应的数据FIFO（40a，40b）仅包含所接收的数据字，没有任何结构化信息。在接收到一个或多个PACKETS之后，设备读取FIFOS，以便重建接收到的数据的原始格式。对于发射机，结构控制FIFO（46a，46b）存储关联数据FIFO（40c，40d）的结构信息，所发送的数据根据结构化信息被构造。接收机和发射机各自包括在从属读和写周期期间耦合在一起的高速内部数据路径（42a，42b）和低速数据路径（54a，54b），并且在高速DMA周期期间被解耦。

5. 发明授权

US4982209A Camera apparatus for detecting code indicia 失效
标题翻译：用于检测代码标记的相机装置
公开(公告)号：US4982209A
公开(公告)日：1991-01-01
申请号：US478873
申请日：1990-02-12
申请人： Robert B. Pearson
发明人： Robert B. Pearson
IPC分类号： G03B7/24
CPC分类号： G03B7/24
摘要： A camera apparatus for detecting code indicia in the form of a series of electrically conductive areas located on the exterior of a film cartridge, includes a loading chamber adapted to receive the cartridge and a plurality of metallic probes which protrude slightly into the chamber to make electrical contact with at least some of the conductive areas of the cartridge. According to the invention, an electrically insulative mounting block has respective securement means equal in actual number to a predetermined number of the conductive areas of the cartridge for permitting the probes to be manually secured selectively to the mounting block, whereby only a minimum number of the probes required for the camera apparatus which is less than the actual number of the securement means need be included in the assembly.
摘要翻译：一种用于检测位于暗盒外部的一系列导电区域形式的代码标记的照相机装置，包括适于容纳盒的装载室和多个金属探针，这些金属探针稍微突出到室中以形成电与盒的至少一些导电区域接触。根据本发明，电绝缘安装块具有实际数量等于盒的预定数量的导电区域的相应的固定装置，用于允许将探头选择性地手动固定到安装块，由此只有最小数量的相机装置所需的探头小于固定装置的实际数量需要包括在组件中。

6. 发明授权

US4844716A Energy releasing catalyst and use thereof 失效
标题翻译：能量释放催化剂及其用途
公开(公告)号：US4844716A
公开(公告)日：1989-07-04
申请号：US261778
申请日：1988-10-24
申请人： Stuart O. Goldman , Robert B. Pearson
发明人： Stuart O. Goldman , Robert B. Pearson
IPC分类号： F23K5/08 , B01J31/12 , B01J37/00 , B01J37/34 , C10L1/12 , C10L10/00
CPC分类号： B01J37/349 , C10L10/02
摘要： A catalyst/substrate delivery system providing a more efficient combustion of hydrocarbon fuels while reducing environmental pollutants emitting therefrom. A light hydrocarbon is misted into a cold environment to form frozen pellets which are then coated with plasma of an atomized catalyst such as platinum, palladium, lithium, zirconium organometals to form microspheres of from about 1 but less than 2000 microns in size.

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