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    • 1. 发明授权
    • Instruction sequencer for parallel operation of functional units
    • 用于并行运行功能单元的指令定序器
    • US4837678A
    • 1989-06-06
    • US35349
    • 1987-04-07
    • Glen J. CullerRobert B. PearsonMichael McCammonWilliam L. ProctorJohn L. Richardson
    • Glen J. CullerRobert B. PearsonMichael McCammonWilliam L. ProctorJohn L. Richardson
    • G06F9/22G06F9/28G06F9/38
    • G06F9/3814G06F9/223G06F9/28G06F9/3802G06F9/3889
    • An instruction sequencer for programming parallel operations of functional units in response to an instruction stream is shown. The instruction sequencer includes a random access memory for storing instruction segments which program the operations of the functional units. An instruction address register contains instruction addresses for selected locations in the memory having instruction segments stored therein. A memory address circuit reads out an instruction stream comprising instruction segments from the memory in response to the stored instruction address and stores the same in an instruction buffer register. A rotating network, which is operatively coupled to the instruction buffer register, rotates the instruction stream so as to position a selected instruction segment at a predetermined location in a rotating network. A control circuit determines whether the rotating network is required to rotate the instruction stream and, if so, directs the rotating network to position the selected instruction segment at the predetermined location in the rotating network. A first decoding circuit receives and decodes the selected instruction segment to produce a first control signal. A shifting circuit receives the rotated instruction stream and shifts the same an amount equal to at least the width of the selected instruction segment and then applies the same to a second decoding circuit which produces a second control signal. The first and second control signals are adapted to be applied to and commence operation of the functional units in parallel.
    • 示出了用于响应于指令流来编程功能单元的并行操作的指令定序器。 指令定序器包括用于存储对功能单元的操作进行编程的指令段的随机存取存储器。 指令地址寄存器包含存储器中存储有指令段的选择位置的指令地址。 存储器地址电路响应于存储的指令地址从存储器读出包括指令段的指令流,并将其存储在指令缓冲寄存器中。 可操作地耦合到指令缓冲寄存器的旋转网络旋转指令流,以将所选择的指令段定位在旋转网络中的预定位置。 控制电路确定旋转网络是否需要旋转指令流,如果是,则引导旋转网络将所选择的指令段定位在旋转网络中的预定位置。 第一解码电路接收并解码所选择的指令段以产生第一控制信号。 移位电路接收旋转的指令流,并移位相等于至少所选指令段的宽度的量,然后将其应用于产生第二控制信号的第二解码电路。 第一和第二控制信号被并行地应用于并开始运行功能单元。
    • 6. 发明授权
    • Method, system, and computer program product for allocating physical memory in a distributed shared memory network
    • 用于在分布式共享存储器网络中分配物理内存的方法,系统和计算机程序产品
    • US06249802B1
    • 2001-06-19
    • US08933829
    • 1997-09-19
    • John L. RichardsonLuis Stevens
    • John L. RichardsonLuis Stevens
    • G06F1322
    • G06F9/5016
    • A method, system, and computer program product for allocating physical memory in a distributed shared memory (DSM) network is provided. Global geometry data is stored that defines a global geometry of nodes in the DSM network. The global geometry data includes node-node distance data and node-resource affinity data. The node-node distance data defines network distances between the nodes for the global geometry of the DSM network. The node-resource affinity data defines resources associated with the nodes in the global geometry of the DSM network. A physical memory allocator searches for a set of nodes in the DSM network that fulfills a memory configuration request based on the global geometry data. The memory configuration request can have parameters that define at least one of a requested geometry, memory amount, and resource affinity. The physical memory allocator in an operating system searches the global geometry data for a set of the nodes within the DSM network that fulfill the memory configuration request and minimize network latency and/or bandwidth. During the search, each node can be evaluated to ensure that the node has sufficient available memory amount and resource affinity. The physical memory allocator can begin a search at locations which are determined based on CPU load, actual memory usage or pseudo-randomly. Faster search algorithms can be used by approximating the DSM network by Boolean cubes.
    • 提供了一种用于在分布式共享存储器(DSM)网络中分配物理存储器的方法,系统和计算机程序产品。 存储定义DSM网络中节点的全局几何的全局几何数据。 全局几何数据包括节点节点距离数据和节点资源关联数据。 节点节点距离数据定义了DSM网络的全局几何结构的节点之间的网络距离。 节点资源关联数据定义与DSM网络的全局几何中的节点相关联的资源。 物理内存分配器搜索DSM网络中的一组基于全局几何数据满足内存配置请求的节点。 存储器配置请求可以具有定义所请求的几何,存储量和资源亲和度中的至少一个的参数。 操作系统中的物理内存分配器在全局几何数据中搜索满足内存配置请求的DSM网络中的一组节点,并最大限度地减少网络延迟和/或带宽。 在搜索期间,可以评估每个节点以确保节点具有足够的可用内存量和资源亲和度。 物理内存分配器可以在基于CPU负载,实际内存使用或伪随机确定的位置开始搜索。 通过使用布尔立方体近似DSM网络可以使用更快的搜索算法。
    • 7. 发明授权
    • Method, system and computer program product for profiling thread virtual
memory accesses
    • 用于剖析线程虚拟内存访问的方法,系统和计算机程序产品
    • US5974536A
    • 1999-10-26
    • US911192
    • 1997-08-14
    • John L. Richardson
    • John L. Richardson
    • G06F11/34G06F9/00G06F12/00
    • G06F11/3466G06F11/3409G06F11/3452G06F2201/815G06F2201/86G06F2201/88
    • A method, system, and computer program product are provided for profiling virtual memory accesses by one or more threads. A virtual memory access thread profiling tool includes a histogram generator and a thread placement file generator. The histogram generator generates a histogram that indicates the relative frequency at which virtual memory addresses are accessed by each program thread. To generate the histogram, the histogram generator runs and interrupts each program thread to collect samples. When an interrupt is issued, a program counter is returned. A valid load or store instruction is determined for a thread in assembly code identified by the returned program counter. In one example, to determine a valid load or store instruction, the histogram generator walks forward or backward through the assembly code identified by the returned program counter until a valid load or store instruction is reached. A virtual memory address corresponding to a valid load or store instruction is then read. A histogram is then incremented based on the virtual memory address to track the relative frequency at which virtual memory addresses are accessed by each thread. Further options are provided to allow a user to control the virtual memory access profiling tool. These options include selecting and setting the type of collection method, selecting and setting program counter (PC) and memory address filtering, setting the sampling granularity, providing start/stop control, selecting real-time graphical histogram output, and naming output files. The virtual memory access thread profiling tool can be implemented as a profiling command executed by an operating system for a multi-processor system, such as, a NUMA machine.
    • 提供了一种方法,系统和计算机程序产品,用于对一个或多个线程的虚拟内存访问进行分析。 虚拟内存访问线程分析工具包括直方图生成器和线程放置文件生成器。 直方图生成器生成一个直方图,指示每个程序线程访问虚拟内存地址的相对频率。 为了生成直方图,直方图生成器运行并中断每个程序线程以收集样本。 当发出中断时,返回一个程序计数器。 对由返回的程序计数器标识的汇编代码中的线程确定有效的加载或存储指令。 在一个示例中,为了确定有效的加载或存储指令,直方图生成器通过返回的程序计数器标识的汇编代码向前或向后移动,直到达到有效的加载或存储指令。 然后读取与有效加载或存储指令相对应的虚拟存储器地址。 然后,基于虚拟存储器地址来增加直方图以跟踪每个线程访问虚拟存储器地址的相对频率。 提供了进一步的选项,以允许用户控制虚拟内存访问分析工具。 这些选项包括选择和设置收集方式的类型,选择和设置程序计数器(PC)和存储器地址过滤,设置采样粒度,提供启动/停止控制,选择实时图形直方图输出和命名输出文件。 虚拟内存访问线程分析工具可以实现为由诸如NUMA机器的多处理器系统的操作系统执行的分析命令。