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1. 发明授权

US07093115B2 Method and apparatus for detecting an interruption in memory initialization 有权
标题翻译：用于检测存储器初始化中断的方法和装置
公开(公告)号：US07093115B2
公开(公告)日：2006-08-15
申请号：US10326394
申请日：2002-12-19
申请人： David I. Poisner , Michael N. Derr , Darren Abramson , Zohar Bogin , Adit Tarmaster , William Knolla
发明人： David I. Poisner , Michael N. Derr , Darren Abramson , Zohar Bogin , Adit Tarmaster , William Knolla
IPC分类号： G06F15/177 , G06F11/22
CPC分类号： G06F9/4403
摘要： Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.
摘要翻译：本发明的实施例提供了一种用于检测存储器初始化中的中断的方法和装置。用于指示存储器初始化是否中断的状态位是否存储在寄存器中。基本输入/输出系统（BIOS）在初始化之前设置状态位，并在初始化后清除状态位。状态位不能通过标准平台复位来复位。在操作中，当系统复位或打开和初始化之前，BIOS检查状态位以检测可能的不正确的存储器初始化。当状态位置位时，BIOS得出结论：存储器初始化尚未完成，因此可能不正确。 BIOS然后使电源循环到存储器，并且采取任何其他步骤来将存储器返回到功能状态。

2. 发明申请

US20080133952A1 Power saving for isochronous data streams in a computer system 有权
标题翻译：节电计算机系统中的同步数据流
公开(公告)号：US20080133952A1
公开(公告)日：2008-06-05
申请号：US11633183
申请日：2006-12-04
申请人： Chai Huat Gan , Darren Abramson , Zohar Bogin
发明人： Chai Huat Gan , Darren Abramson , Zohar Bogin
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3225
摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.
摘要翻译：对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是服务。在此期间，系统DRAM可能会开始刷新。一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。描述和要求保护其他实施例。

3. 发明申请

US20100169883A1 PROVIDING MULTIPLE VIRTUAL DEVICE CONTROLLERS BY REDIRECTING AN INTERRUPT FROM A PHYSICAL DEVICE CONTROLLER 有权
标题翻译：通过重定向物理设备控制器的中断来提供多个虚拟设备控制器
公开(公告)号：US20100169883A1
公开(公告)日：2010-07-01
申请号：US12347970
申请日：2008-12-31
申请人： Zohar Bogin , Suryaprasad Kareenahaili , Rajeev K. Nalawadi , Michael Tabet , Darren Abramson
发明人： Zohar Bogin , Suryaprasad Kareenahaili , Rajeev K. Nalawadi , Michael Tabet , Darren Abramson
IPC分类号： G06F9/455
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/45558 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.
摘要翻译：公开了通过从物理设备控制器重定向中断来提供多个虚拟设备控制器的设备，方法和系统的实施例。在一个实施例中，装置包括处理器，物理设备控制器和虚拟化逻辑。虚拟化逻辑是从物理设备控制器接收第一中断，并且作为响应，从多个虚拟设备控制器之一向处理器发送第二中断。

4. 发明授权

US5889968A Method and apparatus for interlocking a broadcast message on a bus 失效
标题翻译：用于在总线上互锁广播消息的方法和装置
公开(公告)号：US5889968A
公开(公告)日：1999-03-30
申请号：US939801
申请日：1997-09-30
申请人： Joseph A. Bennett , Darren Abramson , Michael Derr , Zohar Bogin
发明人： Joseph A. Bennett , Darren Abramson , Michael Derr , Zohar Bogin
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/36
摘要： A method and apparatus is disclosed for providing an interlocked broadcast message that solves the problem of a system component taking action in response to a broadcast message issued by a processor before the processor receives communication that the broadcast message has been delivered. A broadcast message transaction request is issued from a processor. The broadcast message transaction request is posted in a transaction request buffer. A reply is communicated to the processor that the broadcast message transaction request has been posted, and the broadcast message is then delivered over the bus. In an alternative embodiment, after the broadcast message transaction request is issued from the processor, the broadcast message transaction request is stored in a transaction request buffer. The broadcast message is only delivered over the bus once it has been determined that the reply to the processor that the broadcast message transaction has completed can be immediately delivered to the processor following the delivery of the broadcast message.
摘要翻译：公开了一种用于提供互锁广播消息的方法和装置，其解决了在处理器接收到广播消息已被传送的通信之前响应于由处理器发出的广播消息而采取动作的系统组件的问题。从处理器发出广播消息交易请求。广播消息事务请求被发布在事务请求缓冲器中。向处理器传送广播消息交易请求已经被发布的答复，然后通过总线传送广播消息。在替代实施例中，在从处理器发出广播消息事务请求之后，广播消息事务请求被存储在事务请求缓冲器中。一旦确定广播消息交易已经完成的对处理器的答复可以在传送广播消息之后立即传送到处理器，广播消息仅在总线上传送。

5. 发明授权

US09424211B2 Providing multiple virtual device controllers by redirecting an interrupt from a physical device controller 有权
标题翻译：通过重定向物理设备控制器的中断来提供多个虚拟设备控制器
公开(公告)号：US09424211B2
公开(公告)日：2016-08-23
申请号：US12347970
申请日：2008-12-31
申请人： Zohar Bogin , Suryaprasad Kareenahaili , Rajeev K. Nalawadi , Michael Tabet , Darren Abramson
发明人： Zohar Bogin , Suryaprasad Kareenahaili , Rajeev K. Nalawadi , Michael Tabet , Darren Abramson
IPC分类号： G06F9/455 , G06F13/24 , G06F9/48
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/45558 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.
摘要翻译：公开了通过从物理设备控制器重定向中断来提供多个虚拟设备控制器的设备，方法和系统的实施例。在一个实施例中，装置包括处理器，物理设备控制器和虚拟化逻辑。虚拟化逻辑是从物理设备控制器接收第一中断，并且作为响应，从多个虚拟设备控制器之一向处理器发送第二中断。

6. 发明授权

US07620833B2 Power saving for isochronous data streams in a computer system 有权
标题翻译：节电计算机系统中的同步数据流
公开(公告)号：US07620833B2
公开(公告)日：2009-11-17
申请号：US11633183
申请日：2006-12-04
申请人： Chai Huat Gan , Darren Abramson , Zohar Bogin
发明人： Chai Huat Gan , Darren Abramson , Zohar Bogin
IPC分类号： G06F1/32
CPC分类号： G06F1/3225
摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.
摘要翻译：对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是服务。在此期间，系统DRAM可能会开始刷新。一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。描述和要求保护其他实施例。

7. 发明授权

US07181605B2 Deterministic shut down of memory devices in response to a system warm reset 有权
标题翻译：响应于系统热复位，确定性地关闭存储器件
公开(公告)号：US07181605B2
公开(公告)日：2007-02-20
申请号：US10693226
申请日：2003-10-24
申请人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
发明人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.
摘要翻译：已经公开了响应于系统热复位来确定地关闭存储器件的方法。该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式控制器，其在存储器件初始化之后耦合到存储器件。描述和要求保护其他实施例。

8. 发明授权

US07082480B2 Managing bus transaction dependencies 失效
标题翻译：管理总线事务依赖关系
公开(公告)号：US07082480B2
公开(公告)日：2006-07-25
申请号：US10674944
申请日：2003-09-29
申请人： Zohar Bogin , Serafin E. Garcia
发明人： Zohar Bogin , Serafin E. Garcia
IPC分类号： G06F3/00
CPC分类号： G06F13/24 , G06F13/385
摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.
摘要翻译：在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。

9. 发明授权

US06983339B1 Method and apparatus for processing interrupts of a bus 失效
标题翻译：一种用于处理总线中断的方法和装置
公开(公告)号：US06983339B1
公开(公告)日：2006-01-03
申请号：US09675801
申请日：2000-09-29
申请人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
发明人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
IPC分类号： G06F1/00
CPC分类号： G06F13/24
摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.
摘要翻译：一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。标记为最低优先级可重定向的中断根据任务优先级信息重定向。提供对XTPR事务的支持以更新XTPR寄存器。提供XTPR更新事务和重定向中断的优先顺序。

10. 发明申请

US20050195202A1 Optimized memory addressing 有权
标题翻译：优化的内存寻址
公开(公告)号：US20050195202A1
公开(公告)日：2005-09-08
申请号：US10796686
申请日：2004-03-08
申请人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
IPC分类号： G06F12/00 , G06F12/14 , G06F13/00
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
摘要翻译：本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

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