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1. 发明申请

US20100095038A1 Driver Transparent Message Signaled Interrupts 有权
标题翻译：驱动程序透明消息信号中断
公开(公告)号：US20100095038A1
公开(公告)日：2010-04-15
申请号：US12636027
申请日：2009-12-11
申请人： Joseph A. Bennett
发明人： Joseph A. Bennett
IPC分类号： G06F13/24
CPC分类号： G06F13/4291 , G06F13/24
摘要： Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.
摘要翻译：描述机器可读介质，方法和装置以发出消息信号中断。在一些公开的实施例中，设备以使得能够写入具有水平敏感语义的设备驱动器正确地服务该设备的方式生成消息信号中断，尽管边缘触发特性消息被指示中断。

2. 发明授权

US06907510B2 Mapping of interconnect configuration space 失效
标题翻译：映射互连配置空间
公开(公告)号：US06907510B2
公开(公告)日：2005-06-14
申请号：US10114661
申请日：2002-04-01
申请人： Joseph A. Bennett , Randolph L. Campbell , Prashant Sethi , Jose Vargas
发明人： Joseph A. Bennett , Randolph L. Campbell , Prashant Sethi , Jose Vargas
IPC分类号： G06F9/455 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0292
摘要： A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.
摘要翻译：通过互连来访问与处理器连接的设备的配置数据空间的方法包括从处理器接收访问处理器的可寻址空间的请求。响应于接收到用于访问设备的配置数据空间的指令而产生该请求。访问设备的配置数据空间和处理器的可寻址空间之间的映射，映射先前已将设备的配置数据空间映射到处理器可寻址空间的一个或多个页面。使用该映射，将来自处理器的请求转换为互连上的配置周期以访问设备的配置数据空间。

3. 发明授权

US06901461B2 Hardware assisted ATA command queuing 有权
标题翻译：硬件辅助ATA命令排队
公开(公告)号：US06901461B2
公开(公告)日：2005-05-31
申请号：US10334840
申请日：2002-12-31
申请人： Joseph A. Bennett
发明人： Joseph A. Bennett
IPC分类号： G06F3/06 , G06F13/14 , G06F13/28 , G06F13/38
CPC分类号： G06F13/385 , G06F3/0601 , G06F2003/0692
摘要： One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status. The disk drive can signal that it is ready to execute the programmed command, or it can signal that it is not ready to perform the programmed command but is ready to receive additional command programming information corresponding to another queue entry, or it may signal that it is ready to execute a previously programmed command. The disk drive host controller then performs the required operations using the information stored in the queue without involving the processor. Because the processor is only involved in setting up a command block in system memory and in signaling the disk drive host controller that the command block is ready for reading, the processor is freed up to perform other tasks and overall system performance is improved.
摘要翻译：一个实施例涉及将处理器将用于多个数据事务的磁盘驱动器命令信息写入可高速缓存的系统存储器。然后，处理器对磁盘驱动器主机控制器执行单个写入事务。然后，磁盘驱动器主机控制器发生DMA传输，其中读取位于系统存储器中的命令信息，并将命令信息存储在队列中。一旦主机控制器具有命令信息，它将通过串行互连对具有与队列条目相对应的信息来对磁盘驱动器进行编程。磁盘驱动器在处理命令信息后发出中断信号。磁盘驱动器主机控制器不会将中断转发给处理器，而是自动为中断服务。磁盘驱动器主机控制器从磁盘驱动器读取以确定磁盘驱动器状态。磁盘驱动器可以指示它准备好执行编程的命令，或者它可以发信号通知它没有准备好执行编程的命令，但是准备好接收与另一个队列条目相对应的附加命令编程信息，或者它可以发信号准备执行以前编程的命令。然后，磁盘驱动器主机控制器使用存储在队列中的信息来执行所需的操作，而不涉及处理器。由于处理器仅涉及在系统存储器中设置命令块，并且在向盘驱动器主机控制器发信号通知命令块准备好进行读取时，处理器将被释放以执行其他任务，并提高整体系统性能。

4. 发明授权

US06820141B2 System and method of determining the source of a codec 失效
标题翻译：确定编解码器源的系统和方法
公开(公告)号：US06820141B2
公开(公告)日：2004-11-16
申请号：US09967809
申请日：2001-09-28
申请人： Joseph A. Bennett
发明人： Joseph A. Bennett
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： A system and method to determine a port that a codec is attached is disclosed. An access will be attempted to a codec, and the internal hardware of the host will watch which input port the response comes in on, and log that port for the software. Software can then map that input port to direct memory access/addressing engines in the host such that data streams can be steered to the appropriate application.
摘要翻译：公开了一种用于确定附接有编解码器的端口的系统和方法。将尝试访问编解码器，并且主机的内部硬件将监视响应所在的输入端口，并记录该软件的端口。然后，软件可以将该输入端口映射到主机中的直接存储器访问/寻址引擎，使得数据流可以被引导到适当的应用。

5. 发明授权

US06170033A Forwarding causes of non-maskable interrupts to the interrupt handler 失效
标题翻译：向中断处理程序转发不可屏蔽中断的原因
公开(公告)号：US06170033A
公开(公告)日：2001-01-02
申请号：US08940232
申请日：1997-09-30
申请人： Joseph A. Bennett
发明人： Joseph A. Bennett
IPC分类号： G06F946
CPC分类号： G06F13/24
摘要： The present invention relates to a method and apparatus for directing causes of non-maskable interrupts. The apparatus determines whether a computer system is designed to handle an alternative interrupt such as a SCI interrupt. If the system is capable of handling alternative interrupts, forwarding circuitry forwards the causes of non-maskable interrupts to an alternative interrupt handler. If the system is not capable of handling alternative interrupts, the apparatus forwards the cause of non-maskable interrupts to a NMI handler.
摘要翻译：本发明涉及一种用于指示不可屏蔽中断的原因的方法和装置。该装置确定计算机系统是否被设计为处理诸如SCI中断的替代中断。如果系统能够处理替代中断，则转发电路将不可屏蔽中断的原因转发给另一个中断处理程序。如果系统不能处理替代中断，则该设备将不可屏蔽中断的原因转发给NMI处理程序。

6. 发明授权

US677869A Universal joint. 失效
公开(公告)号：US677869A
公开(公告)日：1901-07-09
申请号：US1900036548
申请日：1900-11-15
申请人： JOSEPH A BENNETT , KINSLER GEORGE B
发明人： KINSLER GEORGE B
CPC分类号： F16D3/36

7. 发明申请

US20150382035A1 METHOD AND APPARATUS FOR LOW JITTER CLOCK RECOVERY IN WIRELESS DISPLAY EXTENSIONS 有权
标题翻译：用于无线显示器扩展中低抖动时钟恢复的方法和装置
公开(公告)号：US20150382035A1
公开(公告)日：2015-12-31
申请号：US13996621
申请日：2011-12-21
申请人： Guoqing Li , Joseph A. Bennett , Gideon Prat , Solomon B. Trainin , Sang-Hee Lee , Vallabhajosyula Z. Somayazulu , George R. Hayek , Pat Brouillette , Dmitrii A. Loukianov
发明人： Guoqing Li , Joseph A. Bennett , Gideon Prat , Solomon B. Trainin , Sang-Hee Lee , Vallabhajosyula Z. Somayazulu , George R. Hayek , Pat Brouillette , Dmitrii A. Loukianov
IPC分类号： H04N21/242 , H04N21/61 , H04N21/43 , H04N21/236
CPC分类号： H04N21/242 , H04N21/23608 , H04N21/4305 , H04N21/6131
摘要： An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.
摘要翻译：提供了一种用于确定程序时钟参考（PCR）值有效性的方法，用于避免不准确的可变延迟引用（VDR）值，并且用于避免无线显示扩展的序列号和分组号之间的数据分组的不匹配。该方法包括确定生成具有可选PCR值，VDR值和有效性指示符的数据分组载体。该方法还可以涉及处理数据分组载波以确定数据分组载波是否具有任选的PCR值。该方法还可以包括至少部分地至少部分地导致至少部分地基于来自数据分组载体的确定的不存在可选PCR值来生成替代PCR值。

8. 发明申请

US20140241380A1 MEDIA STREAM OVER PASS THROUGH MECHANISM 审中-公开
标题翻译：媒体流过机械通过
公开(公告)号：US20140241380A1
公开(公告)日：2014-08-28
申请号：US13992451
申请日：2011-11-17
申请人： Joseph A. Bennett , Guoging Li , Vallabhajosyula S. Somayazulu , George R. Hayek , Gideon Prat , Srikanth Kambhatla
发明人： Joseph A. Bennett , Guoging Li , Vallabhajosyula S. Somayazulu , George R. Hayek , Gideon Prat , Srikanth Kambhatla
IPC分类号： H04L29/06
CPC分类号： H04L69/22 , H04N21/2381 , H04N21/4381 , H04N21/643
摘要： A data packet or payload defined by a first format, is generated and is wrapped with headers as defined by a second format, and is processed through a pass through mechanism for transmission based on the second format. The processing includes adding or encapsulating the payload in the transmission data packet. When receiving the transmitted data packet, the headers may be parsed, and the payload processed.
摘要翻译：产生由第一格式定义的数据分组或有效负载，并且由第二格式定义的报头包裹，并且通过基于第二格式传输的传递机制进行处理。该处理包括将有效载荷添加或封装在传输数据包中。当接收到发送的数据分组时，可以解析报头，并且处理有效载荷。

9. 发明授权

US08166223B2 Apparatuses to provide a message signaled interrupt to generate a PCI express interrupt 有权
标题翻译：提供消息信号中断以产生PCI表达中断的装置
公开(公告)号：US08166223B2
公开(公告)日：2012-04-24
申请号：US12636027
申请日：2009-12-11
申请人： Joseph A. Bennett
发明人： Joseph A. Bennett
IPC分类号： G06F13/24
CPC分类号： G06F13/4291 , G06F13/24
摘要： Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.
摘要翻译：描述机器可读介质，方法和装置以发出消息信号中断。在一些公开的实施例中，设备以使得能够写入具有水平敏感语义的设备驱动器正确地服务该设备的方式生成消息信号中断，尽管边缘触发特性消息被指示中断。

10. 发明授权

US07689745B2 Mechanism for synchronizing controllers for enhanced platform power management 失效
标题翻译：同步控制器以增强平台电源管理的机制
公开(公告)号：US07689745B2
公开(公告)日：2010-03-30
申请号：US11159980
申请日：2005-06-23
申请人： Joseph A. Bennett
发明人： Joseph A. Bennett
IPC分类号： G06F13/00
CPC分类号： G06F13/4059 , G06F1/3209 , G06F1/3215 , Y02D10/151
摘要： In one embodiment, an apparatus to synchronize multiple controllers is disclosed. The apparatus comprises a plurality of controllers, and logic coupled to the plurality of controllers to control one or more controllers of the plurality of controllers to perform fetches simultaneously with one or more other controllers of the plurality of controllers. Other embodiments are also described.
摘要翻译：在一个实施例中，公开了一种同步多个控制器的装置。所述设备包括多个控制器，以及耦合到所述多个控制器的逻辑，以控制所述多个控制器中的一个或多个控制器与所述多个控制器中的一个或多个其他控制器同时执行提取。还描述了其它实施例。

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