专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07741928B1 Frequency modulation using a digital frequency locked loop 有权
标题翻译：使用数字频率锁相环调频
公开(公告)号：US07741928B1
公开(公告)日：2010-06-22
申请号：US12247869
申请日：2008-10-08
申请人： David Cousinard , Philippe Mosch , Lydi Smaini , Randy Tsang , Cao-Thong Tu , Miljan Vuletic
发明人： David Cousinard , Philippe Mosch , Lydi Smaini , Randy Tsang , Cao-Thong Tu , Miljan Vuletic
IPC分类号： H03C3/00 , H03C3/06 , H03L7/06 , H04B1/04
CPC分类号： H04B1/034 , H03C3/095
摘要： Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.
摘要翻译：使用数字频率锁相环（DFLL）进行频率调制（FM）的电路和方法。数字控制振荡器（DCO）基于数字调谐字产生和调整调制信号的频率。 DFLL控制逻辑电路接收调制信号的反馈并产生载波信号字。 Σ-Δ调制器电路接收输入信号并施加抖动以产生抖动输入信号字。加法器电路接收并加法抖动输入信号字和载波信号字以产生数字调谐字。 DFLL控制逻辑电路调整载波信号字以锁定调制信号的载波频率。

2. 发明授权

US07932844B1 Circuits and methods for calibrating a frequency response of a filter 有权
标题翻译：用于校准滤波器频率响应的电路和方法
公开(公告)号：US07932844B1
公开(公告)日：2011-04-26
申请号：US12542504
申请日：2009-08-17
申请人： Thien Huynh , Philippe Mosch , Patrick Clement
发明人： Thien Huynh , Philippe Mosch , Patrick Clement
IPC分类号： H03M1/10
CPC分类号： H03H11/1291 , H03H11/1252
摘要： In one embodiment, the present invention includes an integrated circuit comprising a radio frequency communication channel having a mixer and a programmable analog filter coupled to an output terminal of the mixer. The integrated circuit further comprises a digital-to-analog converter providing an AC signal to the digitally programmable analog filter, an analog-to-digital converter (ADC) coupled to an output terminal of the digitally programmable analog filter, and a digital calibration circuit that adjusts the filter frequency according to measurements calculated from the data from the ADC. During a first calibration phase, the filter frequency is adjusted to a first frequency and a first signal is measured. During a second calibration phase, the filter frequency is adjusted to a second frequency approximately equal to a frequency of the AC signal, and a second signal is measured. The filter frequency is further adjusted based on measured values of the first and second signals.
摘要翻译：在一个实施例中，本发明包括集成电路，其包括具有耦合到混频器的输出端的混频器和可编程模拟滤波器的射频通信信道。集成电路还包括向数字可编程模拟滤波器提供AC信号的数模转换器，耦合到数字可编程模拟滤波器的输出端的模数转换器（ADC）和数字校准电路根据从ADC的数据计算的测量值调整滤波器频率。在第一校准阶段期间，将滤波器频率调整到第一频率并测量第一信号。在第二校准阶段期间，将滤波器频率调整到大致等于AC信号的频率的第二频率，并且测量第二信号。基于第一和第二信号的测量值进一步调整滤波器频率。

3. 发明授权

US07107387B2 Control module comprising a ROM with reduced electrical consumption 失效
标题翻译：控制模块包括具有降低的电消耗的ROM
公开(公告)号：US07107387B2
公开(公告)日：2006-09-12
申请号：US10366725
申请日：2003-02-14
申请人： Philippe Mosch
发明人： Philippe Mosch
IPC分类号： G06F12/00
CPC分类号： G11C7/1006
摘要： A control module (1) having the following elements: a read-only memory (ROM 2), a temporary buffer (6), into which the data of said ROM (2) can be transferred in order to be accessible from outside the control module, a read controller (3), for selecting at each cycle the portions of said ROM transferred into said temporary buffer, wherein the portions selected by said read controller (3) depend on the contents of said ROM. One advantage of the invention is the reduction of the electric consumption, since the ROM does not have to be read when the data are already available in the temporary buffer.
摘要翻译：一种具有以下元件的控制模块（1）：只读存储器（ROM2），临时缓冲器（6），可以将所述ROM（2）的数据传送到其中以便从控制器外部访问模块，读控制器（3），用于在每个周期选择传送到所述临时缓冲器中的所述ROM的部分，其中由所述读控制器（3）选择的部分取决于所述ROM的内容。本发明的一个优点是降低了电耗，因为当数据在临时缓冲器中已经可用时不需要读取ROM。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式