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1. 发明授权

US08600324B1 Circuit and method for adjusting a digitally controlled oscillator 有权
标题翻译：用于调节数字控制振荡器的电路和方法
公开(公告)号：US08600324B1
公开(公告)日：2013-12-03
申请号：US12487425
申请日：2009-06-18
申请人： David Cousinard , Cao-Thong Tu , Miljan Vuletic , Lydi Smaini
发明人： David Cousinard , Cao-Thong Tu , Miljan Vuletic , Lydi Smaini
IPC分类号： H03J7/32 , H04B1/18 , H04B1/06 , H04B7/00 , H04B1/26
CPC分类号： H03J7/18 , H03L7/099
摘要： In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.
摘要翻译：在一个实施例中，本发明包括以不同频率产生振荡信号的方法。该方法包括配置数字控制振荡器（DCO）。 DCO被配置为以第一频率产生振荡信号，并且DCO被配置为以第二频率产生振荡信号。另外，DCO被配置为在转换时段期间从第一频率转换到第二频率。在转换时段期间，DCO激活第二频率并在多个时间间隔期间停用第一频率。用于激活第二频率和停用第一频率的时间间隔从转换时间段的开始到转换时间段的结束继续增加。

2. 发明授权

US07741928B1 Frequency modulation using a digital frequency locked loop 有权
标题翻译：使用数字频率锁相环调频
公开(公告)号：US07741928B1
公开(公告)日：2010-06-22
申请号：US12247869
申请日：2008-10-08
申请人： David Cousinard , Philippe Mosch , Lydi Smaini , Randy Tsang , Cao-Thong Tu , Miljan Vuletic
发明人： David Cousinard , Philippe Mosch , Lydi Smaini , Randy Tsang , Cao-Thong Tu , Miljan Vuletic
IPC分类号： H03C3/00 , H03C3/06 , H03L7/06 , H04B1/04
CPC分类号： H04B1/034 , H03C3/095
摘要： Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.
摘要翻译：使用数字频率锁相环（DFLL）进行频率调制（FM）的电路和方法。数字控制振荡器（DCO）基于数字调谐字产生和调整调制信号的频率。 DFLL控制逻辑电路接收调制信号的反馈并产生载波信号字。 Σ-Δ调制器电路接收输入信号并施加抖动以产生抖动输入信号字。加法器电路接收并加法抖动输入信号字和载波信号字以产生数字调谐字。 DFLL控制逻辑电路调整载波信号字以锁定调制信号的载波频率。

3. 发明申请

US20100005272A1 Virtual memory window with dynamic prefetching support 有权
标题翻译：具有动态预取支持的虚拟内存窗口
公开(公告)号：US20100005272A1
公开(公告)日：2010-01-07
申请号：US11578830
申请日：2005-04-19
申请人： Miljan Vuletic , Laura Pozzi , Paolo Ienne
发明人： Miljan Vuletic , Laura Pozzi , Paolo Ienne
IPC分类号： G06F13/28 , G06F12/02
CPC分类号： G06F12/1081 , G06F9/3877
摘要： Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.
摘要翻译：市场上可重构的系统芯片（RSoC）由完整的处理器和大型现场可编程门阵列（FPGA）组成。后者可用于实现系统胶合逻辑，各种外设和特定于应用的协处理器。对于特定于应用程序的协处理器使用FPGA具有一定的加速电位，但由于将软件应用与协处理器连接的复杂性在实践中较少存在。在本应用中，我们提出了一个由操作系统扩展和硬件组件组成的虚拟化层。它降低了接口的复杂性并增加了可移植性的潜力，同时它还允许协处理器通过虚拟存储器窗口访问用户虚拟内存。在处理器和协处理器之间移动数据的负担从编程器转移到操作系统。

4. 发明授权

US08185696B2 Virtual memory window with dynamic prefetching support 有权
标题翻译：具有动态预取支持的虚拟内存窗口
公开(公告)号：US08185696B2
公开(公告)日：2012-05-22
申请号：US11578830
申请日：2005-04-19
申请人： Miljan Vuletic , Laura Pozzi , Paolo Ienne
发明人： Miljan Vuletic , Laura Pozzi , Paolo Ienne
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F9/3877
摘要： Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.
摘要翻译：市场上可重构的系统芯片（RSoC）由完整的处理器和大型现场可编程门阵列（FPGA）组成。后者可用于实现系统胶合逻辑，各种外设和特定于应用的协处理器。对于特定于应用程序的协处理器使用FPGA具有一定的加速电位，但由于将软件应用与协处理器连接的复杂性在实践中较少存在。在本应用中，我们提出了一个由操作系统扩展和硬件组件组成的虚拟化层。它降低了接口的复杂性并增加了可移植性的潜力，同时它还允许协处理器通过虚拟存储器窗口访问用户虚拟内存。在处理器和协处理器之间移动数据的负担从编程器转移到操作系统。

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