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1. 发明申请

US20140132523A1 Touch Sensing Based On Signal Reflections 审中-公开
标题翻译：基于信号反射的触摸传感
公开(公告)号：US20140132523A1
公开(公告)日：2014-05-15
申请号：US13675724
申请日：2012-11-13
申请人： David Brent Guard , Tsung-Ching Wu , Esat Yilmaz
发明人： David Brent Guard , Tsung-Ching Wu , Esat Yilmaz
IPC分类号： G06F3/041
CPC分类号： G06F3/041 , G06F3/0416
摘要： In one embodiment, a method performed by executing logic embodied by one or more computer-readable non-transitory storage media includes sending a first signal on a first line of a touch sensor. The first line includes a first plurality of electrodes. The method includes receiving a reflection of the first signal on the first line of the touch sensor. The method also includes determining coordinates of a touch on a device comprising the touch sensor in response to receiving the reflection of the first signal.
摘要翻译：在一个实施例中，通过执行由一个或多个计算机可读非暂时存储介质体现的逻辑执行的方法包括在触摸传感器的第一行上发送第一信号。第一行包括第一多个电极。该方法包括在触摸传感器的第一行上接收第一信号的反射。该方法还包括响应于接收到第一信号的反射而确定包括触摸传感器的设备上的触摸的坐标。

2. 发明申请

US20120261242A1 Two-Layer Sensor Stack 有权
标题翻译：双层传感器堆栈
公开(公告)号：US20120261242A1
公开(公告)日：2012-10-18
申请号：US13312405
申请日：2011-12-06
申请人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
发明人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
IPC分类号： H03K17/96
CPC分类号： G06F3/044 , G06F2203/04103 , G06F2203/04112 , Y10T29/49155
摘要： In one embodiment, an method apparatus includes an optically clear adhesive (OCA) layer between a cover sheet and a substrate. The substrate has drive or sense electrodes of a touch sensor disposed on a first surface and a second surface of the substrate. The first surface is opposite the second surface and the drive or sense electrodes are made of a conductive mesh of conductive material including metal.
摘要翻译：在一个实施例中，方法装置包括在覆盖片和衬底之间的光学透明粘合剂（OCA）层。衬底具有布置在衬底的第一表面和第二表面上的触摸传感器的驱动或感测电极。第一表面与第二表面相对，驱动或感测电极由包括金属的导电材料的导电网制成。

3. 发明授权

US08946574B2 Two-layer sensor stack 有权
标题翻译：双层传感器堆叠
公开(公告)号：US08946574B2
公开(公告)日：2015-02-03
申请号：US13312405
申请日：2011-12-06
申请人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
发明人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
IPC分类号： H03K17/96 , G06F3/044
CPC分类号： G06F3/044 , G06F2203/04103 , G06F2203/04112 , Y10T29/49155
摘要： In one embodiment, an method apparatus includes an optically clear adhesive (OCA) layer between a cover sheet and a substrate. The substrate has drive or sense electrodes of a touch sensor disposed on a first surface and a second surface of the substrate. The first surface is opposite the second surface and the drive or sense electrodes are made of a conductive mesh of conductive material including metal.
摘要翻译：在一个实施例中，方法装置包括在覆盖片和衬底之间的光学透明粘合剂（OCA）层。衬底具有布置在衬底的第一表面和第二表面上的触摸传感器的驱动或感测电极。第一表面与第二表面相对，驱动或感测电极由包括金属的导电材料的导电网制成。

4. 发明申请

US20120262412A1 Touch Sensor with a Conductive Line Having Different Widths 审中-公开
标题翻译：触摸传感器具有不同宽度的导电线
公开(公告)号：US20120262412A1
公开(公告)日：2012-10-18
申请号：US13347859
申请日：2012-01-11
申请人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
发明人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
IPC分类号： G06F3/044 , H01H1/10
CPC分类号： G06F3/044 , G06F2203/04103 , G06F2203/04112 , Y10T29/49155
摘要： In one embodiment, a touch sensor includes one or more meshes of conductive material. Each of the meshes includes a plurality of conductive lines. A first one of the conductive lines has a first portion and a second portion. The first portion is wider than the second portion.
摘要翻译：在一个实施例中，触摸传感器包括一个或多个导电材料的网格。每个网格包括多条导线。第一导线具有第一部分和第二部分。第一部分比第二部分宽。

5. 发明申请

US20120262382A1 PANEL 有权
标题翻译：面板
公开(公告)号：US20120262382A1
公开(公告)日：2012-10-18
申请号：US13089061
申请日：2011-04-18
申请人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
发明人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
IPC分类号： G06F3/041 , H05K3/10
CPC分类号： G06F3/044 , G06F2203/04103 , G06F2203/04112 , Y10T29/49155
摘要： An electrode pattern for a position sensing panel may have an array of mesh cells formed by sinusoidaly shaped conductive lines extending between vertices of the mesh cells.
摘要翻译：用于位置感测面板的电极图案可以具有由网格单元的顶点之间延伸的正弦形状导电线形成的网格单元阵列。

6. 发明授权

US08797285B2 Panel 有权
标题翻译：面板
公开(公告)号：US08797285B2
公开(公告)日：2014-08-05
申请号：US13089061
申请日：2011-04-18
申请人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
发明人： David Brent Guard , Esat Yilmaz , Tsung-Ching Wu
IPC分类号： G06F3/0488 , G06F3/04883 , G06F3/044 , G06F3/04886 , G06F3/045
CPC分类号： G06F3/044 , G06F2203/04103 , G06F2203/04112 , Y10T29/49155
摘要： An electrode pattern for a position sensing panel may have an array of mesh cells formed by sinusoidaly shaped conductive lines extending between vertices of the mesh cells.
摘要翻译：用于位置感测面板的电极图案可以具有由网格单元的顶点之间延伸的正弦形状导电线形成的网格单元阵列。

7. 发明授权

US5434815A Stress reduction for non-volatile memory cell 失效
标题翻译：非易失性记忆体的压力降低
公开(公告)号：US5434815A
公开(公告)日：1995-07-18
申请号：US184227
申请日：1994-01-19
申请人： George Smarandoiu , Steven J. Schumann , Tsung-Ching Wu
发明人： George Smarandoiu , Steven J. Schumann , Tsung-Ching Wu
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08
摘要： Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective for grounding the gate of a variable threshold programmable transistor in the memory cell. Power down of the word line is reflected in synchronous power-down of the sense line. Additionally, with power down, the sense amplifier for the particular core memory cell is disconnected from a master latch circuit, which in turn is connected to a slave latch circuit for applying the previous sense amplifier output to an input/output buffer, in order to secure the data sensed in core memory during read operation. The invention further permits reduced word line voltages during erase operation on the sense line and the variable threshold programmable transistor.
摘要翻译：非易失性半导体核心存储器性能通过减少核心存储器单元的应力来增强。在字线控制下，通过选择性地向感测线施加偏置电压来减小应力。字线连接到反相器件，反相器件又连接到有效地将存储器单元中的可变阈值可编程晶体管的栅极接地的晶体管。字线的掉电反映在感测线的同步掉电中。此外，在断电时，用于特定核心存储器单元的读出放大器与主锁存电路断开，主锁存电路又连接到从锁存电路，用于将先前的读出放大器输出施加到输入/输出缓冲器，以便在读取操作期间保护在核心存储器中感测的数据。本发明还允许在感测线和可变阈值可编程晶体管的擦除操作期间减少字线电压。

8. 发明授权

US4970565A Sealed charge storage structure 失效
标题翻译：密封电荷存储结构
公开(公告)号：US4970565A
公开(公告)日：1990-11-13
申请号：US522476
申请日：1990-05-10
申请人： Tsung-Ching Wu , James C. Hu , John Y. Huang
发明人： Tsung-Ching Wu , James C. Hu , John Y. Huang
IPC分类号： G11C16/18 , H01L21/8247 , H01L27/115
CPC分类号： G11C16/18 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A memory cell in an EPROM device which is totally sealed from ultraviolet light by a conductive cover without openings therein for leads to the cell's drain, source and gate. Electrical communication with the source is provided by direct contact with the conductive cover. Access to the drain and floating gate is provided by buried N+ implants, buried N+ layers or N-wells crossing underneath the sides of the cover. The memory cell has a single poly floating gate rather than a stacked floating gate/control gate combination. The buried N+ implant or N-well serves as the control gate and is capacitvely coupled to the floating gate via a thin oxide layer in a coupling area.
摘要翻译： EPROM装置中的存储单元，其通过导电盖完全与紫外线密封，而没有开口用于引导电池的漏极，源极和栅极。通过与导电罩的直接接触来提供与源的电连接。通过掩埋N +植入物，掩埋的N +层或穿过覆盖层两侧的N阱提供对漏极和浮动栅极的访问。存储单元具有单个多晶浮栅，而不是堆叠的浮栅/控制栅组合。埋入的N +注入或N阱用作控制栅极，并且通过耦合区域中的薄氧化物层电容耦合到浮置栅极。

9. 发明授权

US4859619A EPROM fabrication process forming tub regions for high voltage devices 失效
标题翻译： EPROM制造工艺形成用于高压装置的桶区域
公开(公告)号：US4859619A
公开(公告)日：1989-08-22
申请号：US219924
申请日：1988-07-15
申请人： Tsung-Ching Wu , Geeng-Chuan Chern , James C. Hu
发明人： Tsung-Ching Wu , Geeng-Chuan Chern , James C. Hu
IPC分类号： H01L21/762 , H01L21/8247
CPC分类号： H01L27/11526 , H01L21/76218 , H01L27/11546 , Y10S148/126
摘要： A process of fabricating high performance EPROMs in which memory cell devices and high voltage circuit devices are formed in p-type tub regions of high threshold voltage. The tub regions are formed by implanting boron ions in photolithographically defined memory cell and high voltage device areas of a p-type wafer substrate, then subjecting the substrate to a high temperature drive-in. The N-channel isolation field is formed separately and has a lower threshold voltage than the tub regions. The isolation field is formed by implanting boron ions around all device areas, including low voltage device areas, using a nitride mask and a low implantation energy. The wafer is then subjected to an anneal step followed by a field oxidation step. The memory cell and other MOS devices are finally formed in the appropriate defined regions. Since the isolation field's threshold voltage can be adjusted separately from the tub regions, the threshold voltage of the field can be reduced making it possible to reduce the isolation spacing of low voltage devices, reduce parasitic capacitance and increase device speed.
摘要翻译：制造高性能EPROM的方法，其中存储单元器件和高电压电路器件形成在高阈值电压的p型区域中。通过在光刻定义的存储单元中注入硼离子和p型晶片衬底的高电压器件区域，然后使衬底经受高温驱入而形成桶区。 N沟道隔离场分开形成，并且具有比桶区域更低的阈值电压。通过使用氮化物掩模和低注入能量将硼离子注入所有器件区域（包括低电压器件区域）来形成隔离场。然后对晶片进行退火步骤，然后进行场氧化步骤。存储单元和其他MOS器件最终形成在适当的限定区域中。由于隔离场的阈值电压可以与桶区域分开调整，所以可以减小场的阈值电压，从而可以降低低压器件的隔离间隔，降低寄生电容并提高器件速度。

10. 发明授权

US07848151B2 Circuit to control voltage ramp rate 有权
标题翻译：电路控制电压斜坡率
公开(公告)号：US07848151B2
公开(公告)日：2010-12-07
申请号：US12398805
申请日：2009-03-05
申请人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey M. Tsai , Tin-Wai Wong , Tsung-Ching Wu
发明人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey M. Tsai , Tin-Wai Wong , Tsung-Ching Wu
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C7/10 , G11C5/14
CPC分类号： G11C16/12
摘要： A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
摘要翻译：一种编程电路和方法，用于以增量的方式对受控或预定的电压脉冲施加电荷转移到非易失性存储单元的浮置栅极，或者从非易失性存储单元的浮动栅极流出，以控制栅极氧化物两端的整体电压。高于传输阈值电压的电压（例如高于隧道阈值电压）以逐步电荷转移方式施加到浮动栅极或从浮动栅极施加到低于薄氧化物损伤阈值的电压极限。控制整体电压可避免氧化物破坏，提高可靠性。

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