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1. 发明申请

US20050088794A1 Removeable ESD for improving I/O pin bandwidth 审中-公开
标题翻译：可拆卸ESD以改善I / O引脚带宽
公开(公告)号：US20050088794A1
公开(公告)日：2005-04-28
申请号：US10692415
申请日：2003-10-23
申请人： David Boerstler , Gricell Co , Harm Hofstee , Christopher Putnam
发明人： David Boerstler , Gricell Co , Harm Hofstee , Christopher Putnam
IPC分类号： H02H9/04 , H02H5/04
CPC分类号： H02H9/046
摘要： The present invention provides for disconnecting a capacitive path from a device when the capacitive path is no longer needed. Disconnecting a capacitive path when it is no longer needed is beneficial because the existence of a capacitive path limits the speed of the protected device. The device is separated from the capacitive path as a function of the current between the IO pad and a control device.
摘要翻译：本发明提供了当不再需要电容路径时，从设备断开电容路径。不再需要断开电容路径是有益的，因为电容路径的存在限制了受保护设备的速度。器件与电容路径分离，作为IO焊盘和控制器件之间的电流的函数。

2. 发明申请

US20070040620A1 Method of functionality testing for a ring oscillator 失效
标题翻译：环形振荡器的功能测试方法
公开(公告)号：US20070040620A1
公开(公告)日：2007-02-22
申请号：US11204408
申请日：2005-08-16
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133
摘要： A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input. The embodiment further comprises detecting the response to the applied first and second test bit signals at the output of the second inverter, and using the detected responses in providing an evaluation of functionality of the ring oscillator.
摘要翻译：提供了一种用于测试环形振荡器的逻辑功能和电连续性的方法和装置，该环形振荡器包括连接形成闭环的奇数个反相器。在该方法和装置中，通过环形振荡器强制已知的值，以测试其完整的电路路径。因此，提供了环形振荡器的功能的低开销确定性测试。在本发明的有用实施例中，提供了一种用于测试环形振荡器中的功能和电连续性的方法，其中第一测试装置插入在第一反相器的输入端和相邻的第二反相器的输出之间。然后操作第一测试装置以将第一和第二测试位作为输入测试信号施加到第一反相器输入。该实施例还包括检测在第二反相器的输出处对所施加的第一和第二测试位信号的响应，并且使用检测到的响应来提供环形振荡器的功能性的评估。

3. 发明申请

US20060220753A1 Oscillator array with row and column control 有权
标题翻译：具有行和列控制的振荡器阵列
公开(公告)号：US20060220753A1
公开(公告)日：2006-10-05
申请号：US11095895
申请日：2005-03-31
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： H03K3/03
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
摘要翻译：提供了一种电路拓扑结构，可用于创建由通用控制输入确定的不同频率运行的单独调谐的振荡器阵列，以及易于管理的多个组件的设计尺寸变化。提供了一列列和列排列的振荡器阵列。列中的每个振荡器都基于列中的其他振荡器是独特的，基于振荡器和扇出的级数，使得每个振荡器将以唯一的频率工作。阵列中不同列的振荡器可能会通过对这些振荡器的选择的共同设置以及列中的振荡器的物理顺序而不同，以进一步降低注入锁定的可能性。基本延迟单元为每列振荡器提供选择，使得每列可被编程为以与其邻居不同的频率工作。

4. 发明申请

US20070043798A1 Random number generator 失效
标题翻译：随机数发生器
公开(公告)号：US20070043798A1
公开(公告)日：2007-02-22
申请号：US11204402
申请日：2005-08-16
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/001 , H04L9/0869
摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
摘要翻译：提供随机数生成器，方法和计算机程序产品用于产生随机数种子。振荡器阵列内的每个振荡器以不同的频率工作。每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。在一个实施例中，振荡器阵列的输出连接到多输入锁存器。多输入锁存器还接收作为时钟信号的采样信号。时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。

5. 发明申请

US20070236266A1 APPARATUS AND METHOD FOR EXTRACTING A MAXIMUM PULSE WIDTH OF A PULSE WIDTH LIMITER 失效
标题翻译：提取脉冲宽度极限的最大脉冲宽度的装置和方法
公开(公告)号：US20070236266A1
公开(公告)日：2007-10-11
申请号：US11278842
申请日：2006-04-06
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1534 , H03K5/156 , H03K2005/00293
摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.
摘要翻译：提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。第11 / 109,090号（以下简称“090”）。在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

6. 发明申请

US20070126475A1 Method and Apparatus for Semi-Automatic Extraction and Monitoring of Diode Ideality in a Manufacturing Environment 审中-公开
标题翻译：在制造环境中半自动提取和监控二极管理想的方法和装置
公开(公告)号：US20070126475A1
公开(公告)日：2007-06-07
申请号：US11466542
申请日：2006-08-23
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K19/173
CPC分类号： G01R31/2632
摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.
摘要翻译：提供了一种半自动提取二极管理想因子的方法，装置和计算机程序。传统上，二极管的电流/电压曲线为理想因素外推提供了基础，必须用手来确定。通过采用与绝对温度（PTAT）发生器成比例的热电压与提取机制，理想因子可以半自动提取。因此，可以采用可靠，快速和便宜的装置来改善理想因素的测量。

7. 发明申请

US20070079197A1 Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance 有权
标题翻译：用于自动自校准占空比电路以实现最大芯片性能的装置和方法
公开(公告)号：US20070079197A1
公开(公告)日：2007-04-05
申请号：US11242677
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R31/28
CPC分类号： H03K5/1565 , G01R31/31727 , G01R31/3187
摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.
摘要翻译：提供一种用于自动校准占空比电路以实现最大性能的装置和方法。提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

8. 发明申请

US20060232310A1 System and method for on/off-chip characterization of pulse-width limiter outputs 失效
标题翻译：用于脉宽限幅器输出的片外特性的系统和方法
公开(公告)号：US20060232310A1
公开(公告)日：2006-10-19
申请号：US11109090
申请日：2005-04-19
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/156 , G01R31/31708 , G01R31/31725 , H03K5/05 , H03K5/26
摘要： The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.
摘要翻译：本发明提供了用于表征脉冲宽度限制器输出的方法。接收已知的时钟信号。所接收的已知时钟信号的脉冲宽度通过第一脉冲宽度限制器来限制，以产生第一中间信号。第一中间信号被延迟已知的量以产生第一延迟信号。第一中间信号被反相以产生第一反相信号。通过第二脉冲宽度限幅器限制第一反相信号的脉冲宽度以产生第二中间信号。第二中间信号被延迟已知的量以产生第二延迟信号。对第一延迟信号和第二延迟信号执行逻辑或运算以产生时钟输出信号。

9. 发明申请

US20050261866A1 Thermal protection for a VLSI chip through reduced c4 usage 审中-公开
标题翻译：通过减少c4的使用，对VLSI芯片进行热保护
公开(公告)号：US20050261866A1
公开(公告)日：2005-11-24
申请号：US10850401
申请日：2004-05-20
申请人： David Boerstler , Hiroki Kihara , Robert Putney , Daniel Stasiak , Michael Wang
发明人： David Boerstler , Hiroki Kihara , Robert Putney , Daniel Stasiak , Michael Wang
IPC分类号： G01R31/26 , G01K7/01 , G01R31/28 , G06F15/00
CPC分类号： G01K7/01
摘要： The present invention provides for determining a temperature in a chip. A voltage across a thermal diode is generated. It is then determined whether the voltage across the first thermal diode exceeds a threshold value. The voltage is correlated with a range of values. The determination of whether the voltage across the thermal diode exceeds the threshold value is correlated with the correlation of the voltage with a range of values. Through the use of voltage level sensors, the use of C4 input/output pins are avoided.
摘要翻译：本发明提供用于确定芯片中的温度。产生热二极管两端的电压。然后确定第一热二极管两端的电压是否超过阈值。电压与值的范围相关。确定热二极管上的电压是否超过阈值与电压与一定范围的值的相关性相关。通过使用电压电平传感器，可以避免使用C4输入/输出引脚。

10. 发明申请

US20050248376A1 CIRCUIT FOR COMPENSATING LPF CAPACITOR CHARGE LEAKAGE IN PHASE LOCKED LOOP SYSTEMS 有权
标题翻译：用于补偿相位锁定环路系统中LPF电容充电电流的电路
公开(公告)号：US20050248376A1
公开(公告)日：2005-11-10
申请号：US10840562
申请日：2004-05-06
申请人： David Boerstler , Eskinder Hailu
发明人： David Boerstler , Eskinder Hailu
IPC分类号： H03L7/00 , H03L7/06 , H03L7/089 , H03L7/093
CPC分类号： H03L7/093 , H03L7/0891
摘要： The present invention provides for a low pass filter. A first capacitor, has a first associated leakage current. A second capacitor has a specified capacitance that is a fraction of the capacitance of the first capacitor, the second capacitor further having a second associated leakage current. A voltage follower circuit is coupled to the output of the first and second capacitor. First and second current sources are coupled to the voltage follower circuit. A bias current source is coupled the first current source. A current mirror is coupled to the second current source, and the current mirror is further coupled to at least the anode of the first capacitor, thereby generating replacement current of a capacitor within a low-pass filter.
摘要翻译：本发明提供一种低通滤波器。第一电容器具有第一相关泄漏电流。第二电容器具有指定电容，其是第一电容器的电容的一部分，第二电容器还具有第二相关联的漏电流。电压跟随器电路耦合到第一和第二电容器的输出。第一和第二电流源耦合到电压跟随器电路。偏置电流源耦合第一电流源。电流镜耦合到第二电流源，并且电流镜还被耦合到至少第一电容器的阳极，从而产生低通滤波器内的电容器的替换电流。

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