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1. 发明申请

US20070236266A1 APPARATUS AND METHOD FOR EXTRACTING A MAXIMUM PULSE WIDTH OF A PULSE WIDTH LIMITER 失效
标题翻译：提取脉冲宽度极限的最大脉冲宽度的装置和方法
公开(公告)号：US20070236266A1
公开(公告)日：2007-10-11
申请号：US11278842
申请日：2006-04-06
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1534 , H03K5/156 , H03K2005/00293
摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.
摘要翻译：提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。第11 / 109,090号（以下简称“090”）。在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

2. 发明申请

US20070126475A1 Method and Apparatus for Semi-Automatic Extraction and Monitoring of Diode Ideality in a Manufacturing Environment 审中-公开
标题翻译：在制造环境中半自动提取和监控二极管理想的方法和装置
公开(公告)号：US20070126475A1
公开(公告)日：2007-06-07
申请号：US11466542
申请日：2006-08-23
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K19/173
CPC分类号： G01R31/2632
摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.
摘要翻译：提供了一种半自动提取二极管理想因子的方法，装置和计算机程序。传统上，二极管的电流/电压曲线为理想因素外推提供了基础，必须用手来确定。通过采用与绝对温度（PTAT）发生器成比例的热电压与提取机制，理想因子可以半自动提取。因此，可以采用可靠，快速和便宜的装置来改善理想因素的测量。

3. 发明申请

US20070079197A1 Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance 有权
标题翻译：用于自动自校准占空比电路以实现最大芯片性能的装置和方法
公开(公告)号：US20070079197A1
公开(公告)日：2007-04-05
申请号：US11242677
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R31/28
CPC分类号： H03K5/1565 , G01R31/31727 , G01R31/3187
摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.
摘要翻译：提供一种用于自动校准占空比电路以实现最大性能的装置和方法。提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

4. 发明申请

US20060232310A1 System and method for on/off-chip characterization of pulse-width limiter outputs 失效
标题翻译：用于脉宽限幅器输出的片外特性的系统和方法
公开(公告)号：US20060232310A1
公开(公告)日：2006-10-19
申请号：US11109090
申请日：2005-04-19
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/156 , G01R31/31708 , G01R31/31725 , H03K5/05 , H03K5/26
摘要： The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.
摘要翻译：本发明提供了用于表征脉冲宽度限制器输出的方法。接收已知的时钟信号。所接收的已知时钟信号的脉冲宽度通过第一脉冲宽度限制器来限制，以产生第一中间信号。第一中间信号被延迟已知的量以产生第一延迟信号。第一中间信号被反相以产生第一反相信号。通过第二脉冲宽度限幅器限制第一反相信号的脉冲宽度以产生第二中间信号。第二中间信号被延迟已知的量以产生第二延迟信号。对第一延迟信号和第二延迟信号执行逻辑或运算以产生时钟输出信号。

5. 发明申请

US20050248376A1 CIRCUIT FOR COMPENSATING LPF CAPACITOR CHARGE LEAKAGE IN PHASE LOCKED LOOP SYSTEMS 有权
标题翻译：用于补偿相位锁定环路系统中LPF电容充电电流的电路
公开(公告)号：US20050248376A1
公开(公告)日：2005-11-10
申请号：US10840562
申请日：2004-05-06
申请人： David Boerstler , Eskinder Hailu
发明人： David Boerstler , Eskinder Hailu
IPC分类号： H03L7/00 , H03L7/06 , H03L7/089 , H03L7/093
CPC分类号： H03L7/093 , H03L7/0891
摘要： The present invention provides for a low pass filter. A first capacitor, has a first associated leakage current. A second capacitor has a specified capacitance that is a fraction of the capacitance of the first capacitor, the second capacitor further having a second associated leakage current. A voltage follower circuit is coupled to the output of the first and second capacitor. First and second current sources are coupled to the voltage follower circuit. A bias current source is coupled the first current source. A current mirror is coupled to the second current source, and the current mirror is further coupled to at least the anode of the first capacitor, thereby generating replacement current of a capacitor within a low-pass filter.
摘要翻译：本发明提供一种低通滤波器。第一电容器具有第一相关泄漏电流。第二电容器具有指定电容，其是第一电容器的电容的一部分，第二电容器还具有第二相关联的漏电流。电压跟随器电路耦合到第一和第二电容器的输出。第一和第二电流源耦合到电压跟随器电路。偏置电流源耦合第一电流源。电流镜耦合到第二电流源，并且电流镜还被耦合到至少第一电容器的阳极，从而产生低通滤波器内的电容器的替换电流。

6. 发明申请

US20070260409A1 Duty Cycle Measurement Apparatus and Method 审中-公开
标题翻译：占空比测量装置及方法
公开(公告)号：US20070260409A1
公开(公告)日：2007-11-08
申请号：US11777370
申请日：2007-07-13
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.
摘要翻译：提供了一种用于测量诸如微处理器或片上系统的集成电路器件中被测信号占空比的机构。该机制产生与占空比成比例的频率，可以使用普通实验室或制造设备测量。该机构可以使用标准互补金属氧化物半导体工艺中的简单电路来实现，其需要非常小的面积并且可以在不使用时关闭电源。该机构可以包括例如低通滤波器，用于提供校准参考电压信号的分压器，电压到频率转换器，用于分频频率信号输出的分频器，使得信号的频率在预定范围内，以及输出驱动器和输出板。从频率输出信号，可以使用片外设备来计算被测信号的占空比。

7. 发明申请

US20070255517A1 METHOD AND APPARATUS FOR ON-CHIP DUTY CYCLE MEASUREMENT 失效
标题翻译：用于芯片周期测量的方法和装置
公开(公告)号：US20070255517A1
公开(公告)日：2007-11-01
申请号：US11380982
申请日：2006-05-01
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R31/31727 , G01R31/3004 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译：所公开的方法和装置测量时钟电路提供给位于“片上”的占空比测量（DCM）电路的参考时钟信号的占空比，即集成电路（IC），其中并入DCM电路。在一个实施例中，DCM电路包括由电荷泵驱动的电容器。参考时钟信号驱动电荷泵。时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。控制软件访问数据存储，以确定测试时钟信号对应的占空比。

8. 发明申请

US20070081406A1 APPARATUS AND METHOD FOR PROVIDING A REPROGRAMMABLE ELECTRICALLY PROGRAMMABLE FUSE 有权
标题翻译：提供可编程可编程保险丝的装置和方法
公开(公告)号：US20070081406A1
公开(公告)日：2007-04-12
申请号：US11246586
申请日：2005-10-07
申请人： David Boerstler , Eskinder Hailu , Subramanian Iyer , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Subramanian Iyer , Jieming Qi
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/16
摘要： An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to be programmed, a first programming current is applied to a first eFuse to thereby increase the resistance of the first eFuse by an incremental amount. When the pair of eFuses is to be returned to an unprogrammed state, a second programming current source is applied to a second eFuse to thereby increase a resistance of the second eFuse to be greater than the resistance of the first eFuse. When the sensing current is applied to the eFuses, a difference in the resulting voltages across the eFuses is identified and used to indicate whether the reprogrammable eFuse is in a programmed state or unprogrammed state.
摘要翻译：提供了一种用于提供可再编程电可编程熔丝（eFuse）的设备和方法。利用该装置和方法，提供一对耦合到编程电流源并感测电流源的eFuses。当要对一对eFuse进行编程时，将第一编程电流施加到第一eFuse，从而增加第一eFuse的电阻增量。当一对eFuse将返回到未编程状态时，第二编程电流源被施加到第二eFuse，从而将第二eFuse的电阻增加到大于第一eFuse的电阻。当感应电流被施加到eFuse时，识别出eFuses上产生的电压的差异，并用于指示可重新编程的eFuse是否处于编程状态或未编程状态。

9. 发明申请

US20070057697A1 Apparatus and method for verifying glitch-free operation of a multiplexer 失效
公开(公告)号：US20070057697A1
公开(公告)日：2007-03-15
申请号：US11227026
申请日：2005-09-15
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R29/02
CPC分类号： G01R31/31708 , G01R31/31725
摘要： An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.

10. 发明申请

US20070040620A1 Method of functionality testing for a ring oscillator 失效
标题翻译：环形振荡器的功能测试方法
公开(公告)号：US20070040620A1
公开(公告)日：2007-02-22
申请号：US11204408
申请日：2005-08-16
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133
摘要： A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input. The embodiment further comprises detecting the response to the applied first and second test bit signals at the output of the second inverter, and using the detected responses in providing an evaluation of functionality of the ring oscillator.
摘要翻译：提供了一种用于测试环形振荡器的逻辑功能和电连续性的方法和装置，该环形振荡器包括连接形成闭环的奇数个反相器。在该方法和装置中，通过环形振荡器强制已知的值，以测试其完整的电路路径。因此，提供了环形振荡器的功能的低开销确定性测试。在本发明的有用实施例中，提供了一种用于测试环形振荡器中的功能和电连续性的方法，其中第一测试装置插入在第一反相器的输入端和相邻的第二反相器的输出之间。然后操作第一测试装置以将第一和第二测试位作为输入测试信号施加到第一反相器输入。该实施例还包括检测在第二反相器的输出处对所施加的第一和第二测试位信号的响应，并且使用检测到的响应来提供环形振荡器的功能性的评估。

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