专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060288134A1 Data streamer 有权
公开(公告)号：US20060288134A1
公开(公告)日：2006-12-21
申请号：US11224738
申请日：2005-09-12
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath , John Poole
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath , John Poole
IPC分类号： G06F5/00
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

2. 发明授权

US06434649B1 Data streamer 有权
标题翻译：数据流
公开(公告)号：US06434649B1
公开(公告)日：2002-08-13
申请号：US09173297
申请日：1998-10-14
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath
IPC分类号： G06F1300
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从预定数量接收地址和数据信息的模块，包括内存和I / O设备。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

3. 发明授权

US07051123B1 Data transfer engine of a processor having a plurality of modules 有权
标题翻译：具有多个模块的处理器的数据传输引擎
公开(公告)号：US07051123B1
公开(公告)日：2006-05-23
申请号：US09710192
申请日：2000-11-10
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , Ashok Raman , Eric Rehm , Radhika Thekkath
IPC分类号： G06F3/00
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

4. 发明授权

US06347344B1 Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor 有权
标题翻译：集成多媒体系统与本地处理器，数据传输交换机，处理模块，固定功能单元，数据流，接口单元和多路复用器，均集成在多媒体处理器
公开(公告)号：US06347344B1
公开(公告)日：2002-02-12
申请号：US09172286
申请日：1998-10-14
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F300
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A multiplexer is coupled to the interface unit and provides access between a selected number of I/O device driver units and external I/O devices via output pins. A plurality of external I/O devices are coupled to the multimedia processor.
摘要翻译：集成多媒体系统具有设置在集成电路中的多媒体处理器。该系统包括耦合到多媒体处理器的第一主机处理器系统。第二本地处理器被布置在控制多媒体处理器的操作的多媒体处理器内。数据传输开关设置在多媒体处理器内并且耦合到第二处理器，该第二处理器将数据传送到多媒体处理器的各个模块。固定功能单元设置在所述多媒体处理器内，耦合到所述第二处理器和所述数据传输开关，并且被配置为执行三维图形操作。数据流器耦合到所述数据传输开关，并且被配置为调度在多个模块根据相应的信道分配设置在多媒体处理器内。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多路复用器耦合到接口单元，并通过输出引脚提供所选数量的I / O设备驱动单元和外部I / O设备之间的访问。多个外部I / O设备耦合到多媒体处理器。

5. 发明授权

US07457890B2 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US07457890B2
公开(公告)日：2008-11-25
申请号：US11589695
申请日：2006-10-30
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F3/00 , G06F15/76 , G06F1/00 , G06F15/16 , G06F13/14
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.
摘要翻译：具有多媒体处理器的集成多媒体系统被布置在具有耦合到多媒体处理器的第一主处理器系统的集成电路中，以及设置在多媒体处理器内的用于控制多媒体处理器的操作的第二本地处理器。数据传输开关耦合到第二处理器，用于将数据传送到处理器的各个模块，其中至少一个是数据高速缓存。数据传输交换机在缓存和处理器内的模块之间的任一方向上传输数据。数据流器根据相应的信道分配来调度在多媒体处理器内布置的各个模块之间的同时数据传输。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多个外部I / O设备经由多路复用器耦合到多个I / O设备驱动器单元。

6. 发明授权

US07272670B2 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US07272670B2
公开(公告)日：2007-09-18
申请号：US09777003
申请日：2001-02-05
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F3/00 , G06F15/76 , G06F1/00 , G06F15/16 , G06F13/14
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.
摘要翻译：集成多媒体系统具有设置在集成电路中的多媒体处理器。处理器被布置在控制多媒体处理器的操作的多媒体处理器内。数据传输交换机设置在多媒体处理器内并且耦合到处理器，该处理器将数据传送到多媒体处理器的各个模块。固定功能单元设置在多媒体处理器内，耦合到处理器和数据传输开关。数据流器耦合到数据传输交换机，并且被配置为根据相应的信道分配来调度在多媒体处理器内设置的多个模块之间的同时数据传输。由于接口单元耦合到数据流器并且具有多个I / O设备驱动器单元。耦合到接口单元的多路复用器通过输出引脚提供所选数量的I / O设备驱动器单元和外部I / O设备之间的访问。

7. 发明申请

US20070130401A1 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US20070130401A1
公开(公告)日：2007-06-07
申请号：US11589695
申请日：2006-10-30
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F13/38
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.
摘要翻译：具有多媒体处理器的集成多媒体系统被布置在具有耦合到多媒体处理器的第一主处理器系统的集成电路中，以及设置在多媒体处理器内的用于控制多媒体处理器的操作的第二本地处理器。数据传输开关耦合到第二处理器，用于将数据传送到处理器的各个模块，其中至少一个是数据高速缓存。数据传输交换机在缓存和处理器内的模块之间的任一方向上传输数据。数据流器根据相应的信道分配来调度在多媒体处理器内布置的各个模块之间的同时数据传输。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多个外部I / O设备经由多路复用器耦合到多个I / O设备驱动器单元。

8. 发明授权

US06560674B1 Data cache system 失效
公开(公告)号：US06560674B1
公开(公告)日：2003-05-06
申请号：US09172646
申请日：1998-10-14
申请人： Koji Hosogi , Gregorio Gervasio , Yatin Mundkur , Radhika Thekkath
发明人： Koji Hosogi , Gregorio Gervasio , Yatin Mundkur , Radhika Thekkath
IPC分类号： G06F1200
CPC分类号： G06F12/0835 , G06F12/0833 , G06F12/0875
摘要： An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式