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1. 发明授权

US5372973A Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology 失效
标题翻译：使用化学机械抛光技术在冷阴极发射器尖端周围形成自对准栅极结构的方法
公开(公告)号：US5372973A
公开(公告)日：1994-12-13
申请号：US53794
申请日：1993-04-27
申请人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
发明人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
IPC分类号： H01J1/304 , H01J9/02 , H01L21/3105 , H01L21/465
CPC分类号： H01J9/025 , H01L21/31053 , H01J2201/30426 , H01J2201/319 , H01J2209/0226
摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.
摘要翻译：用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii）化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料。

2. 发明授权

US5300463A Method of selectively etching silicon dioxide dielectric layers on semiconductor wafers 失效
标题翻译：在半导体晶片上选择性地蚀刻二氧化硅电介质层的方法
公开(公告)号：US5300463A
公开(公告)日：1994-04-05
申请号：US847368
申请日：1992-03-06
申请人： David A. Cathey , J. Brett Rolfson
发明人： David A. Cathey , J. Brett Rolfson
IPC分类号： H01L21/311 , H01L21/00 , H01L21/02 , H01L21/465
CPC分类号： H01L21/31111
摘要： A method of utilizing and etching SiO.sub.2 in the processing of semiconductor wafers comprises: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) providing a layer of doped SiO.sub.2 atop the layer of undoped SiO.sub.2 ; and c) wet etching the layer of doped SiO.sub.2 selectively relative to the undoped layer of SiO.sub.2 utilizing an acid solution, the acid solution comprising a mixture of at least two different mineral acids provided in a selected ratio relative to one another, one of the mineral acids being HF. The preferred volumetric ratio of other mineral acids in the acid solution to HF in the acid solution is from 20:1 to 110:1, with a ratio of from 45:1 to 65:1 being most preferred. Example acids to be combined with the HF include H.sub.2 SO.sub.4, HCl, HNO.sub.3, H.sub.3 PO.sub.4, HBr, HI, HClO.sub.4, and HIO.sub.4, or mixtures thereof.
摘要翻译：在半导体晶片的处理中利用和蚀刻SiO 2的方法包括：a）在晶片顶上提供未掺杂的SiO 2层; b）在未掺杂的SiO 2层的顶部提供掺杂SiO 2层; 和c）使用酸溶液相对于未掺杂的SiO 2层选择性地浸蚀掺杂SiO 2层，所述酸溶液包含以相对于彼此的选定比率提供的至少两种不同的无机酸的混合物，所述矿物质之一酸是HF。在酸溶液中酸溶液中的其它无机酸与HF的优选体积比为20:1至110:1，最优选的比例为45:1至65:1。与HF组合的实例酸包括H 2 SO 4，HCl，HNO 3，H 3 PO 4，HBr，HI，HClO 4和HIO 4，或其混合物。

3. 发明授权

US5229331A Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology 失效
标题翻译：使用化学机械抛光技术在冷阴极发射器尖端周围形成自对准栅极结构的方法
公开(公告)号：US5229331A
公开(公告)日：1993-07-20
申请号：US837453
申请日：1992-02-14
申请人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
发明人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
IPC分类号： H01J1/304 , H01J9/02 , H01L21/3105
CPC分类号： H01J9/025 , H01L21/31053 , H01J2201/30426 , H01J2201/319 , H01J2209/0226
摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.
摘要翻译：用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii）化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料。

4. 发明授权

US6013943A Etch stop for use in etching of silicon oxide 失效
标题翻译：蚀刻停止用于蚀刻氧化硅
公开(公告)号：US6013943A
公开(公告)日：2000-01-11
申请号：US850461
申请日：1997-05-05
申请人： David A. Cathey , J. Brett Rolfson , Valerie A. Ward , Karen M. Winchester
发明人： David A. Cathey , J. Brett Rolfson , Valerie A. Ward , Karen M. Winchester
IPC分类号： H01L21/311 , H01L21/318 , H01L23/58
CPC分类号： H01L21/31116 , H01L21/3185 , Y10S438/97
摘要： A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
摘要翻译：用于氧化硅干氟蚀刻工艺中的蚀刻停止层由氮化物制成，其中以氢键连接在其中，其形式为N-H键，O-H键或截留的游离氢。蚀刻停止层是通过在标准PECVD氮化硅制造工艺中增加NH 3流，降低SiH4流量，降低氮气流量或全部三种来制备的。替代地，蚀刻停止可以通过在PECVD工艺或LPCVD工艺中脉冲RF场来制造。

5. 发明授权

US5372901A Removable bandpass filter for microlithographic aligners 失效
标题翻译：用于微光刻对准器的可移动带通滤光片
公开(公告)号：US5372901A
公开(公告)日：1994-12-13
申请号：US927210
申请日：1992-08-05
申请人： J. Brett Rolfson , David A. Cathey
发明人： J. Brett Rolfson , David A. Cathey
IPC分类号： G03F1/00 , G03F1/26 , G03F7/20 , G03F9/00
CPC分类号： G03F1/26 , G03F7/70575
摘要： A removable bandpass filter layer (22), which is preferably part of a pattern transfer tool (10), improves the resolution of a semiconductor wafer aligner that uses a relatively broad bandwidth radiation source. A narrower bandwidth filter layer provides more complete destructive interference of undesirable diffraction patterns when it is used with a phase-shift pattern transfer tool and removes radiation of longer wavelengths to improve resolution when it is used with a nonphase-shift pattern transfer tool. Using a removable bandpass filter layer, rather than permanently installing a narrow bandpass filter in the aligner, does not affect the speed of patterning layers that do not require the enhanced resolution. The same aligner can thus be used for either high resolution or high throughput without substantial modification to the aligner.
摘要翻译：优选为图案转印工具（10）的一部分的可拆卸带通滤光层（22）提高了使用相对宽的带宽辐射源的半导体晶片对准器的分辨率。较窄的带宽滤波器层当与相移图案转移工具一起使用时，提供更为完整的不希望的衍射图形的相消干涉，并且当与非相移图案转印工具一起使用时，可以去除较长波长的辐射以提高分辨率。使用可拆卸的带通滤光层，而不是在对准器中永久性安装窄带通滤光片，不会影响不需要增强分辨率的图案层的速度。因此，相同的对准器可以用于高分辨率或高通量而不对对准器进行实质修改。

6. 发明授权

US5358599A Process for etching a semiconductor device using an improved protective etching mask 失效
标题翻译：使用改进的保护蚀刻掩模蚀刻半导体器件的工艺
公开(公告)号：US5358599A
公开(公告)日：1994-10-25
申请号：US84394
申请日：1993-06-29
申请人： David A. Cathey , J. Brett Rolfson
发明人： David A. Cathey , J. Brett Rolfson
IPC分类号： H01L21/30 , H01L21/02 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/306 , B44C1/22
CPC分类号： H01L28/40 , H01L21/0274 , H01L21/3081 , H01L21/31144 , H01L21/32139 , Y10S438/948
摘要： The subject process relates to the etching of a semiconductor device having a re-entrant profile area which causes residual positive photoresist material to remain therewithin after formation of an etch mask of the positive photoresist material. A negative photoresist etch mask is formed on a major surface of the outer conductive film structural layer. The etch mask comprises a plurality of photoresist lines arranged in a predetermined pattern which defines a plurality of spaces therebetween, which in turn expose a plurality of areas of the major surface of the semiconductor device. Substantially all of the negative photosensitive material located within the re-entrant profile area is removed during the etch mask formation process. The exposed areas of the major surface of the outer structural layer can then be etched to form the requisite etch pattern with a chemical etchant system without regard to interference by unwanted residual photoresist material.
摘要翻译：本发明涉及一种半导体器件的蚀刻，该半导体器件具有在形成正型光致抗蚀剂材料的蚀刻掩模之后残留的正性光致抗蚀剂材料保留在其中的重新设计的轮廓区域。在外导电膜结构层的主表面上形成负光致抗蚀剂蚀刻掩模。蚀刻掩模包括以预定图案布置的多个光致抗蚀剂线，其限定了它们之间的多个间隔，其又暴露半导体器件的主表面的多个区域。在蚀刻掩模形成工艺期间，基本上所有位于重入轮廓区域内的负感光材料都被去除。然后可以用化学蚀刻剂系统蚀刻外部结构层的主表面的暴露区域以形成必要的蚀刻图案，而不考虑不想要的残留光致抗蚀剂材料的干扰。

7. 发明授权

US5329207A Field emission structures produced on macro-grain polysilicon substrates 失效
标题翻译：在大颗粒多晶硅基板上产生的场致发射结构
公开(公告)号：US5329207A
公开(公告)日：1994-07-12
申请号：US883629
申请日：1992-05-13
申请人： David A. Cathey , J. Brett Rolfson , Tyler A. Lowrey , Trung T. Doan
发明人： David A. Cathey , J. Brett Rolfson , Tyler A. Lowrey , Trung T. Doan
IPC分类号： H01J1/30 , H01J1/304 , H01J9/02 , H01J29/04 , H01J31/12
CPC分类号： H01J1/3042 , H01J9/025 , H01J2201/30407
摘要： A baseplate for a flat panel display comprising relatively thick semiconductor substrate, wherein the semiconductor substrate is a macro-grain polycrystalline substrate, which is amorphized by ion implantation or reformed by recrystallization, to obscure the grain boundaries, thereafter redundant circuitry may be fabricated thereon to further enhance product yield.
摘要翻译：一种用于平板显示器的底板，包括相对厚的半导体衬底，其中半导体衬底是通过离子注入而非晶化或通过重结晶重新形成的宏晶多晶衬底，以掩盖晶界，此后可制造冗余电路，进一步提高产品产量。

8. 发明授权

US06222257B1 Etch stop for use in etching of silicon oxide 有权
标题翻译：蚀刻停止用于蚀刻氧化硅
公开(公告)号：US06222257B1
公开(公告)日：2001-04-24
申请号：US09370080
申请日：1999-08-06
申请人： David A. Cathey , J. Brett Rolfson , Valerie A. Ward , Karen M. Winchester
发明人： David A. Cathey , J. Brett Rolfson , Valerie A. Ward , Karen M. Winchester
IPC分类号： H01L2358
CPC分类号： H01L21/31116 , H01L21/3185 , Y10S438/97
摘要： A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, Si—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
摘要翻译：用于氧化硅干氟蚀刻工艺中的蚀刻停止层由氮化物制成，其中以N-H键，Si-H键或截留的游离氢的形式掺入氢。蚀刻停止层是通过在标准PECVD氮化硅制造工艺中增加NH 3流，降低SiH4流量，降低氮气流量或全部三种来制备的。替代地，蚀刻停止可以通过在PECVD工艺或LPCVD工艺中脉冲RF场来制造。

9. 发明授权

US5259799A Method to form self-aligned gate structures and focus rings 失效
标题翻译：形成自对准栅极结构和聚焦环的方法
公开(公告)号：US5259799A
公开(公告)日：1993-11-09
申请号：US977477
申请日：1992-11-17
申请人： Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
发明人： Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
IPC分类号： H01J9/02 , H01J9/04
CPC分类号： H01J9/025 , H01J2209/0226 , H01J2329/00
摘要： A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.
摘要翻译：用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极和聚焦环结构的选择性蚀刻和化学机械平面化工艺，其中发射尖端i）可选地通过氧化锐化，ii）沉积有第一保留层，iii）沉积有导电材料层，iv）沉积有第二共形绝缘层，v）沉积有焦点电极环材料层，vi）任选地沉积有缓冲材料，vii）用化学机械平面化（CMP）步骤，以暴露第二共形层的一部分，viii）蚀刻以形成自对准栅极和聚焦环，从而暴露发射极尖端，之后xi）发射极尖端可以被涂覆有低功函数材料。

10. 发明授权

US5232549A Spacers for field emission display fabricated via self-aligned high energy ablation 失效
标题翻译：用于通过自对准高能量消融制造的场发射显示的间隔物
公开(公告)号：US5232549A
公开(公告)日：1993-08-03
申请号：US869348
申请日：1992-04-14
申请人： David A. Cathey , Chris C. Yu , Trung T. Doan , Tyler A. Lowrey , J. Brett Rolfson
发明人： David A. Cathey , Chris C. Yu , Trung T. Doan , Tyler A. Lowrey , J. Brett Rolfson
IPC分类号： H01J9/24 , G03F7/00 , H01J9/18 , H01J31/12
CPC分类号： H01J9/242 , G03F7/0007 , H01J31/123 , H01J9/185 , H01J2329/8625 , H01J2329/864
摘要： Fabrication of spacer supports for use in flat panel displays through a process which involves 1) depositing an insulating material on an electrode plate, 2) optionally, patterning a reflective material superjacent the insulating material, 3) irradiating the electrode plate, and thereby removing the exposed insulating material, 4) optionally, removing the reflective material, and thereby exposing the remaining insulative material which will serve as the spacer supports, after which the plate can be aligned with a complementary electrode plate, and a vacuum formed therebetween.
摘要翻译：通过涉及1）在电极板上沉积绝缘材料的方法制造用于平板显示器的间隔支架，2）可选地，在绝缘材料之上图案化反射材料，3）照射电极板，从而去除暴露的绝缘材料，4）任选地，去除反射材料，从而暴露作为间隔件支撑件的剩余绝缘材料，之后可以将板与互补电极板对准，并在其间形成真空。

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