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1. 发明授权

US06768694B2 Method of electrically blowing fuses under control of an on-chip tester interface apparatus 有权
标题翻译：在片上测试仪接口装置的控制下电熔熔丝的方法
公开(公告)号：US06768694B2
公开(公告)日：2004-07-27
申请号：US10265591
申请日：2002-10-07
申请人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
发明人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C700
CPC分类号： G11C29/027 , G11C17/18 , G11C29/56 , G11C29/785 , G11C2029/1208
摘要： A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.
摘要翻译：公开了一种芯片修复系统，专为自动化测试设备而独立应用于许多独特的非常密集的ASIC设备，在高周转环境中。在测试期间，系统将控制芯片内置的自检（BIST）引擎收集和压缩修复数据，程序保险丝，并最终解压缩并重新加载后保险丝测试的修复数据。在最终使用应用程序中，该系统在上电时或在系统请求下解压缩加载修复数据。

2. 发明授权

US07916826B2 Diagnostic method and apparatus for non-destructively observing latch data 有权
标题翻译：用于非破坏性观察锁存数据的诊断方法和装置
公开(公告)号：US07916826B2
公开(公告)日：2011-03-29
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

3. 发明申请

US20090180584A1 DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA 有权
标题翻译：诊断方法和装置，用于非分析性观察数据
公开(公告)号：US20090180584A1
公开(公告)日：2009-07-16
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

4. 发明授权

US06656751B2 Self test method and device for dynamic voltage screen functionality improvement 失效
标题翻译：用于动态电压屏幕功能改进的自检方法和装置
公开(公告)号：US06656751B2
公开(公告)日：2003-12-02
申请号：US09683050
申请日：2001-11-13
申请人： John E. Andersen , Bruce M. Cowan , Pamela S. Gillis , Steven F. Oakland , Michael R. Ouellette
发明人： John E. Andersen , Bruce M. Cowan , Pamela S. Gillis , Steven F. Oakland , Michael R. Ouellette
IPC分类号： H01L2100
CPC分类号： G11C29/12015 , G01R31/31724 , G01R31/3187 , G11C29/14 , H03K5/135
摘要： Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.
摘要翻译：公开了一种包括内置自检控制器的装置，其具有用于提供指示是否正在执行动态电压屏幕（DVS）测试的接口信号的机制。自检控制器与包括具有时钟速度的时钟的存储器阵列相关联。存储器阵列还包括时钟调节器，当接口信号指示正在执行DVS测试时，时钟调节器接收接口信号并降低时钟速度。

5. 发明授权

US07089136B2 Method for reduced electrical fusing time 失效
标题翻译：降低电熔时间的方法
公开(公告)号：US07089136B2
公开(公告)日：2006-08-08
申请号：US10604414
申请日：2003-07-18
申请人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
发明人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G01R31/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output of the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain when the next fuse(s) is not to be blown. Accordingly, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.
摘要翻译：一种电熔丝回路设计，用于减少用冗余eFuse电路制造的半导体器件的测试时间。除了熔丝锁存器和图案锁存器之外，每个eFuse电路还提供一对二路复用器（MUX）。保险丝图案锁存器中存储有要熔断保险丝的信息。模式锁存器的输出与程序输入进行“与”运算以提供MUX的选择信号。基于选择信号，MUX允许移位的“1”进入移位链中的下一个锁存器，或者在下一个保险丝不被熔断时，旁路下一个锁存器或锁存在换档链中。因此，本发明仅能够使与熔断器相关联的熔丝锁存器保持被转换的“1”传播到下一个eFuse电路。

6. 发明授权

US07453973B2 Diagnostic method and apparatus for non-destructively observing latch data 失效
标题翻译：用于非破坏性观察锁存数据的诊断方法和装置
公开(公告)号：US07453973B2
公开(公告)日：2008-11-18
申请号：US11533907
申请日：2006-09-21
申请人： Darren L. Anand , John R. Goss , Peter O. Jacobsen , Michael R. Ouellette , Thomas G. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jacobsen , Michael R. Ouellette , Thomas G. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

7. 发明授权

US07243279B2 Method for separating shift and scan paths on scan-only, single port LSSD latches 失效
标题翻译：用于在仅扫描单端口LSSD锁存器上分离移位和扫描路径的方法
公开(公告)号：US07243279B2
公开(公告)日：2007-07-10
申请号：US10604908
申请日：2003-08-26
申请人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
发明人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.
摘要翻译：一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

8. 发明授权

US06922649B2 Multiple on-chip test runs and repairs for memories 失效
标题翻译：多个片上测试运行和修复记忆
公开(公告)号：US06922649B2
公开(公告)日：2005-07-26
申请号：US10721561
申请日：2003-11-25
申请人： Krishnendu Mondal , Michael R. Ouellette
发明人： Krishnendu Mondal , Michael R. Ouellette
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G01R31/28 , G06F19/00 , G11C7/00 , G11C29/00 , G11C29/44
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/72 , G11C29/789 , G11C2029/1208
摘要： A structure and method for performing on-chip test runs and repairs of a memory chip. In the first test run and repair, a BIST circuit obtains the original combined repair solution from a fuse bay on the memory chip, runs the first test run for the memory chip, obtains a first test-run repair solution, and combines the original combined repair solution and the first test-run repair solution to obtain the latest/first combined repair solution. Then, an exclusive-OR gate is used to compare the first combined repair solution and the original combined repair solution to obtain a first new repair solution, which is programmed into the fuses of the fuse bay. As a result, the fuse bay stores the first combined repair solution. In the second test run and repair, a similar process is performed, and so on. As a result, any number of test runs and repairs can be performed on-chip for the memory chip.
摘要翻译：一种用于进行片上测试的结构和方法，其运行和维修存储芯片。在第一次测试运行和修复中，BIST电路从存储器芯片上的保险丝架获取原始的组合修复解决方案，运行第一个测试运行的内存芯片，获得第一个测试运行的修复解决方案，并结合原始组合修理解决方案和第一个测试维修解决方案，以获得最新/第一次组合修复解决方案。然后，使用异或门来比较第一个组合修复解决方案和原始组合修复解决方案，以获得第一个新的修复解决方案，该解决方案被编程到保险丝座的保险丝中。因此，保险丝架存储第一个组合的维修解决方案。在第二次测试运行和修复中，执行类似的过程，等等。因此，对于存储器芯片，可以在芯片上执行任何数量的测试运行和维修。

9. 发明授权

US06928377B2 Self-test architecture to implement data column redundancy in a RAM 有权
公开(公告)号：US06928377B2
公开(公告)日：2005-08-09
申请号：US10658940
申请日：2003-09-09
申请人： Steven M. Eustis , Krishnendu Mondal , Michael R. Ouellette , Jeremy P. Rowland
发明人： Steven M. Eustis , Krishnendu Mondal , Michael R. Ouellette , Jeremy P. Rowland
IPC分类号： G01R31/28 , G01R31/00 , G06F19/00 , G11C29/00 , G11C29/12 , G11C29/44
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/1208
摘要： Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.

10. 发明授权

US07305600B2 Partial good integrated circuit and method of testing same 有权
标题翻译：部分良好的集成电路及其测试方法
公开(公告)号：US07305600B2
公开(公告)日：2007-12-04
申请号：US10651874
申请日：2003-08-29
申请人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St.Pierre , Tad J. Wilder , Carl F. Barnhart
发明人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St.Pierre , Tad J. Wilder , Carl F. Barnhart
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
摘要翻译：一种集成电路，包括：多个宏电路，每个宏电路具有相同的功能; 包含多个保险丝的保险丝库，保险丝的状态存储测试数据，至少指示哪些宏电路测试失败; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

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