专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07038950B1 Multi bit program algorithm 有权
标题翻译：多位程序算法
公开(公告)号：US07038950B1
公开(公告)日：2006-05-02
申请号：US10982296
申请日：2004-11-05
申请人： Darlene Hamilton , Ed Hsia , Pau-Ling Chen
发明人： Darlene Hamilton , Ed Hsia , Pau-Ling Chen
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/3418 , G11C16/3431 , G11C16/349 , G11C2211/5621
摘要： Methods of programming NEW data into unprogrammed bits of a group of memory cells is provided. The method applies an interactive programming algorithm that individually verifies and programs the NEW data, reference (REF) data, and existing or OLD data. OLD data is separately verified to a compensated program verify level from that of the NEW data to improve memory reliability and insure minimal uniform stress levels to the array. The improved programming algorithm prevents older data from being needlessly refreshed, thus mitigating stress to the cells that eventually causes the data areas to decay at different rates and become prematurely unreliable.
摘要翻译：提供将新数据编程到一组存储器单元的未编程位中的方法。该方法应用一种交互式编程算法，可以对新数据，参考（REF）数据和现有或OLD数据进行单独验证和编程。 OLD数据被分别验证为与NEW数据的补偿程序验证级别，以提高内存可靠性并确保阵列的最小均匀应力水平。改进的编程算法防止老化的数据被不必要地刷新，从而减轻细胞的压力，最终导致数据区域以不同的速率衰减并变得过早地不可靠。

2. 发明授权

US06791880B1 Non-volatile memory read circuit with end of life simulation 有权
标题翻译：非易失性存储器读取电路，具有寿命终止模拟
公开(公告)号：US06791880B1
公开(公告)日：2004-09-14
申请号：US10431320
申请日：2003-05-06
申请人： Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
发明人： Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C16/04 , G11C16/349 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
摘要翻译：具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源参考电流源。来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流或骑自行车。

3. 发明申请

US20050276120A1 Erase algorithm for multi-level bit flash memory 有权
标题翻译：多级位闪存的擦除算法
公开(公告)号：US20050276120A1
公开(公告)日：2005-12-15
申请号：US10864947
申请日：2004-06-10
申请人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
发明人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
IPC分类号： G11C11/56 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3413 , G11C11/5635 , G11C16/3404 , G11C16/3409
摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.
摘要翻译：提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到对应于单元的期望的最终阈值电压值的最终数据状态。可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

4. 发明授权

US07251158B2 Erase algorithm for multi-level bit flash memory 有权
标题翻译：多级位闪存的擦除算法
公开(公告)号：US07251158B2
公开(公告)日：2007-07-31
申请号：US10864947
申请日：2004-06-10
申请人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
发明人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
IPC分类号： G11C11/34
CPC分类号： G11C16/3413 , G11C11/5635 , G11C16/3404 , G11C16/3409
摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.
摘要翻译：提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到与单元的期望的最终阈值电压值对应的最终数据状态。可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

5. 发明授权

US07009887B1 Method of determining voltage compensation for flash memory devices 有权
标题翻译：确定闪存器件电压补偿的方法
公开(公告)号：US07009887B1
公开(公告)日：2006-03-07
申请号：US10860450
申请日：2004-06-03
申请人： Ed Hsia , Darlene Hamilton , Alykhan Madhani , Kenneth Yu
发明人： Ed Hsia , Darlene Hamilton , Alykhan Madhani , Kenneth Yu
IPC分类号： G11C16/04
CPC分类号： G11C29/021 , G11C16/04 , G11C16/12 , G11C29/028 , G11C29/50004
摘要： The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the determined or identified programming variations for the group to which the given memory cell belongs. These adjusted programming variations facilitate successful programming of the particular memory cell.
摘要翻译：本发明确定或识别阵列或存储设备内的不同组的编程变化，其适当地编程各组内的存储单元。然后，在给定存储单元的编程操作期间，根据给定存储器单元所属的组的确定或识别的编程变化来应用编程电压。这些调整的编程变化有助于特定存储器单元的成功编程。

6. 发明授权

US07440333B2 Method of determining voltage compensation for flash memory devices 有权
标题翻译：确定闪存器件电压补偿的方法
公开(公告)号：US07440333B2
公开(公告)日：2008-10-21
申请号：US11340916
申请日：2006-01-27
申请人： Ed Hsia , Darlene Hamilton , Alykhan Madhani , Kenneth Yu
发明人： Ed Hsia , Darlene Hamilton , Alykhan Madhani , Kenneth Yu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C29/021 , G11C16/04 , G11C16/12 , G11C29/028 , G11C29/50004
摘要： The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the determined or identified programming variations for the group to which the given memory cell belongs. These adjusted programming variations facilitate successful programming of the particular memory cell.
摘要翻译：本发明确定或识别阵列或存储设备内的不同组的编程变化，其适当地编程各组内的存储单元。然后，在给定存储单元的编程操作期间，根据给定存储器单元所属的组的确定或识别的编程变化来应用编程电压。这些调整的编程变化有助于特定存储器单元的成功编程。

7. 发明申请

US20060120151A1 Method of determining voltage compensation for flash memory devices 有权
公开(公告)号：US20060120151A1
公开(公告)日：2006-06-08
申请号：US11340916
申请日：2006-01-27
申请人： Ed Hsia , Darlene Hamilton , Alykhan Madhani , Kenneth Yu
发明人： Ed Hsia , Darlene Hamilton , Alykhan Madhani , Kenneth Yu
IPC分类号： G11C16/06
CPC分类号： G11C29/021 , G11C16/04 , G11C16/12 , G11C29/028 , G11C29/50004
摘要： The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the determined or identified programming variations for the group to which the given memory cell belongs. These adjusted programming variations facilitate successful programming of the particular memory cell.

8. 发明授权

US08941094B2 Methods for adjusting the conductivity range of a nanotube fabric layer 有权
标题翻译：调整纳米管织物层电导率范围的方法
公开(公告)号：US08941094B2
公开(公告)日：2015-01-27
申请号：US12874501
申请日：2010-09-02
申请人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
发明人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
IPC分类号： H01L45/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/00 , H01L51/44
CPC分类号： H01L45/149 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/0015 , H01L51/0048 , H01L51/444 , Y02E10/549
摘要： Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
摘要翻译：公开了调整和/或限制纳米管织物层的电导率范围的方法。在一些方面，通过湿法化学技术使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过等离子体处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过CVD处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，纳米管织物层的导电性通过惰性离子注入物官能化织物层内的纳米管元件来调节。

9. 发明授权

US08264898B2 Controlling AC disturbance while programming 有权
标题翻译：在编程时控制交流干扰
公开(公告)号：US08264898B2
公开(公告)日：2012-09-11
申请号：US13156763
申请日：2011-06-09
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

10. 发明申请

US20110235412A1 CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
标题翻译：控制交流干扰编程
公开(公告)号：US20110235412A1
公开(公告)日：2011-09-29
申请号：US13156763
申请日：2011-06-09
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式