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1. 发明授权

US09337047B2 Semiconductor device and method of making semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US09337047B2
公开(公告)日：2016-05-10
申请号：US11856086
申请日：2007-09-17
申请人： Danny Pak-Chum Shum , Ronald Kakoschke , John Power , Wolfram Langheinrich
发明人： Danny Pak-Chum Shum , Ronald Kakoschke , John Power , Wolfram Langheinrich
IPC分类号： H01L29/788 , H01L21/4763 , H01L21/28 , H01L27/105 , H01L27/115 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28273 , H01L27/105 , H01L27/11526 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.
摘要翻译：一个或多个实施例涉及半导体器件，包括：高K电介质材料; 以及设置在所述高k电介质材料上的氮掺杂硅材料。

2. 发明申请

US20090072292A1 SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20090072292A1
公开(公告)日：2009-03-19
申请号：US11856086
申请日：2007-09-17
申请人： Danny Pak-Chum Shum , Ronald Kakoschke , John Power , Wolfram Langheinrich
发明人： Danny Pak-Chum Shum , Ronald Kakoschke , John Power , Wolfram Langheinrich
IPC分类号： H01L29/788 , H01L21/4763
CPC分类号： H01L21/28273 , H01L27/105 , H01L27/11526 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.
摘要翻译：一个或多个实施例涉及半导体器件，包括：高K电介质材料; 以及设置在所述高k电介质材料上的氮掺杂硅材料。

3. 发明申请

US20100203703A1 Deep Trench Isolation Structures and Methods of Formation Thereof 有权
标题翻译：深沟槽隔离结构及其形成方法
公开(公告)号：US20100203703A1
公开(公告)日：2010-08-12
申请号：US12702368
申请日：2010-02-09
申请人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
发明人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
IPC分类号： H01L21/762
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/11521 , H01L27/11546
摘要： Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要翻译：公开了深沟槽隔离结构及其形成方法。描述了用于增加形成在深沟槽隔离结构附近的寄生晶体管的阈值电压的几种方法和结构，包括将沟道阻挡区域注入深沟槽隔离结构的底表面，部分地填充深沟槽隔离的底部具有绝缘材料的结构，和/或用掺杂的多晶硅材料填充至少一部分深沟槽隔离结构。

4. 发明授权

US08258028B2 Deep trench isolation structures and methods of formation thereof 有权
标题翻译：深沟槽隔离结构及其形成方法
公开(公告)号：US08258028B2
公开(公告)日：2012-09-04
申请号：US12702368
申请日：2010-02-09
申请人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
发明人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
IPC分类号： H01L21/763
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/11521 , H01L27/11546
摘要： Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要翻译：公开了深沟槽隔离结构及其形成方法。描述了用于增加形成在深沟槽隔离结构附近的寄生晶体管的阈值电压的几种方法和结构，包括将沟道阻挡区域注入深沟槽隔离结构的底表面，部分地填充深沟槽隔离的底部具有绝缘材料的结构，和/或用掺杂的多晶硅材料填充至少一部分深沟槽隔离结构。

5. 发明申请

US20070075434A1 Method for producing a PCM memory element and corresponding PCM memory element 审中-公开
标题翻译：用于产生PCM存储器元件和相应PCM存储元件的方法
公开(公告)号：US20070075434A1
公开(公告)日：2007-04-05
申请号：US11522225
申请日：2006-09-15
申请人： Ronald Kakoschke , Danny Pak-Chum Shum
发明人： Ronald Kakoschke , Danny Pak-Chum Shum
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： The invention relates to a method for producing a PCM memory element and to a corresponding PCM element. The method of production comprises the following steps: providing a first and a second line device (Ma, Mb) underneath an insulating layer (10); providing a hole (5a, 5b) in the insulation layer (10), which partially exposes the first and the second line device (Ma, Mb); providing, as the respective lower electrode, a respective strip-shaped resistor element (20; 20′; 20″) on the wall of the hole (5a, 5b), which electrically contacts the exposed first or second line device (Ma, Mb): providing a filling (30) from an insulating material in the hole (5a, 5b) between the strip-shaped resistor elements (20; 20′; 20″); providing a layer (35) produced from a PCM material in the hole (5a, 5b), which electrically contacts the strip-shaped resistor elements (20; 20′; 20″) on their upper faces; providing a conducting layer (40) above the hole (5a, 5b) and the surrounding surface of the insulating layer (10): forming a sublithographic masking strip (50) on the conducting layer (40) above the hole (5a, 5b) and the surrounding surface of the insulating layer (210) at an angle to the direction of the first and second line device (Ma, Mb): forming segments of the mask strip (50); structuring the conducting layer (40) and the layer (35) produced from the PCM material while using the segments for forming the respective upper electrode from the conducting layer (40) and a PCM area of the layer (35) produced from PCM material lying between the upper and the lower electrode: removing the mask strip (50); and electrically connecting the upper electrode to an additional line device (80).
摘要翻译：本发明涉及一种用于产生PCM存储器元件和相应的PCM元件的方法。该生产方法包括以下步骤：在绝缘层（10）下方提供第一和第二线路器件（Ma，Mb）; 在所述绝缘层（10）中设置部分地暴露所述第一和第二线路装置（Ma，Mb）的孔（5a，5b）; 在孔（5a，5b）的壁上提供与暴露的第一或第二线路装置（Ma）电接触的相应的带状电阻器元件（20; 20'; 20“）作为相应的下电极， Mb）：从带状电阻器元件（20,20'; 20“）之间的孔（5a，5b）中的绝缘材料提供填充物（30）; 在所述孔（5a，5b）中提供由PCM材料制成的层（35），所述层与所述带状电阻器元件（20; 20'; 20“）电气接触; 在所述孔（5a，5b）上方和所述绝缘层（10）的周围表面上提供导电层（40）：在所述孔（5a）上方的导电层（40）上形成亚光刻掩模条（50），5b）和绝缘层（210）的周围表面与第一和第二线路装置（Ma，Mb）的方向成角度：形成掩模条（50）的段; 构造由导电层（40）形成导电层（40）和由PCM材料制成的层（35），同时使用用于从导电层（40）形成相应上电极的段和由PCM材料制成的层（35）的PCM区域在所述上电极和所述下电极之间：去除所述掩模条（50）; 以及将所述上部电极电连接到附加线路装置（80）。

6. 发明授权

US07679130B2 Deep trench isolation structures and methods of formation thereof 有权
标题翻译：深沟槽隔离结构及其形成方法
公开(公告)号：US07679130B2
公开(公告)日：2010-03-16
申请号：US11367247
申请日：2006-03-03
申请人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
发明人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
IPC分类号： H01L27/115
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/11521 , H01L27/11546
摘要： Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要翻译：公开了深沟槽隔离结构及其形成方法。描述了用于增加形成在深沟槽隔离结构附近的寄生晶体管的阈值电压的几种方法和结构，包括将沟道阻挡区域注入深沟槽隔离结构的底表面，部分地填充深沟槽隔离的底部具有绝缘材料的结构，和/或用掺杂的多晶硅材料填充至少一部分深沟槽隔离结构。

7. 发明授权

US08039904B2 Apparatus of memory array using finfets 有权
标题翻译：使用finfets的存储器阵列的装置
公开(公告)号：US08039904B2
公开(公告)日：2011-10-18
申请号：US12784526
申请日：2010-05-21
申请人： Ronald Kakoschke , Klaus Schruefer
发明人： Ronald Kakoschke , Klaus Schruefer
IPC分类号： H01L21/021
CPC分类号： H01L27/1052 , H01L21/84 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L29/41791 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/141
摘要： A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
摘要翻译：存储单元包括FinFET选择装置和存储元件。在一些实施例中，存储器单元具有耦合在鳍片的表面和存储元件之间的接触元件。

8. 发明授权

US07978504B2 Floating gate device with graphite floating gate 有权
标题翻译：带石墨浮动门的浮闸装置
公开(公告)号：US07978504B2
公开(公告)日：2011-07-12
申请号：US12131938
申请日：2008-06-03
申请人： Ronald Kakoschke , Harald Seidl
发明人： Ronald Kakoschke , Harald Seidl
IPC分类号： G11C11/00
CPC分类号： H01L21/28282 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/4966
摘要： One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.
摘要翻译：一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述基板上的电荷存储层; 以及设置在所述电荷存储层上的控制栅极，其中所述电荷存储层或所述控制栅极层包含碳同素异形体。

9. 发明授权

US07915662B2 Integrated memory device having columns having multiple bit lines 有权
公开(公告)号：US07915662B2
公开(公告)日：2011-03-29
申请号：US10918335
申请日：2004-08-13
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L29/788
摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

10. 发明申请

US20100317162A1 METHOD FOR PRODUCING AN INTEGRATED FIELD-EFFECT TRANSISTOR 有权
标题翻译：用于生成集成场效应晶体管的方法
公开(公告)号：US20100317162A1
公开(公告)日：2010-12-16
申请号：US12848576
申请日：2010-08-02
申请人： Ronald Kakoschke
发明人： Ronald Kakoschke
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/7855 , H01L29/78612
摘要： A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.
摘要翻译：提供了一种用于制造场效应晶体管的方法。该方法包括形成衬底区域，在衬底区域形成两个端子区域，一个端子区域是源极区域，另一个端子区域是漏极区域，形成两个电绝缘绝缘层，它们布置在并且与控制区域相邻，形成导电连接区域，该导电连接区域将导电连接区域和基板区域导电地连接到包含金属 - 半导体化合物的导电连接区域，在形成之后通过化学机械抛光来平整表面控制区域，在抛光之后蚀刻回控制区域，并且在蚀刻后区域，基板区域和端子区域上进行用于形成金属 - 半导体化合物的自对准方法。

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