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1. 发明申请

US20110188524A1 DESIGNS AND PROCESSES FOR THERMALLY STABILIZING A VERTICAL CAVITY SURFACE EMITTING LASER (VCSEL) IN A CHIP-SCALE ATOMIC CLOCK 有权
标题翻译：用于热稳定垂直孔表面激光（VCSEL）的芯片尺寸原子钟的设计和工艺
公开(公告)号：US20110188524A1
公开(公告)日：2011-08-04
申请号：US12884489
申请日：2010-09-17
申请人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley , Linda J. Forner
发明人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley , Linda J. Forner
IPC分类号： H01S3/04 , H01S1/00
CPC分类号： H01S5/183 , G04F5/14 , H01S5/005 , H01S5/02 , H01S5/02208 , H01S5/02296 , H01S5/02453 , H01S5/02476
摘要： Designs and processes for thermally stabilizing a vertical cavity surface emitting laser (vcsel) in a chip-scale atomic clock are provided. In one embodiment, a Chip-Scale Atomic Clock includes: a vertical cavity surface emitting laser (vcsel); a heater block coupled to a base of the vcsel; a photo detector; a vapor cell, wherein the vapor cell includes a chamber that defines at least part of an optical path for laser light between the vcsel and the photo detector; and an iso-thermal cage surrounding the vcsel on all sides, the iso-thermal cage coupled to the heater block via a thermally conductive path.
摘要翻译：提供了在芯片级原子钟中热稳定垂直腔表面发射激光器（vcsel）的设计和工艺。在一个实施例中，芯片级原子钟包括：垂直腔表面发射激光器（vcsel）; 耦合到所述vcsel的基座的加热器块; 光电检测器蒸汽池，其中所述蒸汽池包括限定用于所述vcsel和所述光电检测器之间的激光的光路的至少一部分的室; 以及围绕所有侧面上的vcsel的等温保持架，通过导热路径耦合到加热器块的等热笼。

2. 发明授权

US08218590B2 Designs and processes for thermally stabilizing a vertical cavity surface emitting laser (vcsel) in a chip-scale atomic clock 有权
标题翻译：用于在芯片级原子钟中热稳定垂直腔表面发射激光器（vcsel）的设计和工艺
公开(公告)号：US08218590B2
公开(公告)日：2012-07-10
申请号：US12884489
申请日：2010-09-17
申请人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley , Linda J. Forner
发明人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley , Linda J. Forner
IPC分类号： H01S3/04
CPC分类号： H01S5/183 , G04F5/14 , H01S5/005 , H01S5/02 , H01S5/02208 , H01S5/02296 , H01S5/02453 , H01S5/02476
摘要： Designs and processes for thermally stabilizing a vertical cavity surface emitting laser (vcsel) in a chip-scale atomic clock are provided. In one embodiment, a Chip-Scale Atomic Clock includes: a vertical cavity surface emitting laser (vcsel); a heater block coupled to a base of the vcsel; a photo detector; a vapor cell, wherein the vapor cell includes a chamber that defines at least part of an optical path for laser light between the vcsel and the photo detector; and an iso-thermal cage surrounding the vcsel on all sides, the iso-thermal cage coupled to the heater block via a thermally conductive path.
摘要翻译：提供了在芯片级原子钟中热稳定垂直腔表面发射激光器（vcsel）的设计和工艺。在一个实施例中，芯片级原子钟包括：垂直腔表面发射激光器（vcsel）; 耦合到所述vcsel的基座的加热器块; 光电检测器蒸汽池，其中所述蒸汽池包括限定用于所述vcsel和所述光电检测器之间的激光的光路的至少一部分的室; 以及围绕所有侧面上的vcsel的等温保持架，通过导热路径耦合到加热器块的等热笼。

3. 发明授权

US08067991B2 Chip-scale atomic clock with two thermal zones 有权
标题翻译：具有两个热区的芯片级原子钟
公开(公告)号：US08067991B2
公开(公告)日：2011-11-29
申请号：US12891441
申请日：2010-09-27
申请人： Daniel W. Youngner , Jeff A. Ridley , Mary K. Salit , Son T. Lu , Linda J. Forner
发明人： Daniel W. Youngner , Jeff A. Ridley , Mary K. Salit , Son T. Lu , Linda J. Forner
IPC分类号： H01S1/06 , H03B17/00
CPC分类号： G04F5/145 , H01S5/005 , H01S5/02 , H01S5/02208 , H01S5/02296 , H01S5/02453 , H01S5/02476 , H01S5/183
摘要： A chip-scale atomic clock comprises a physics package and a laser die located in a first thermal zone of the physics package. A quarter wave plate is mounted in the physics package and is in optical communication with the laser die. A vapor cell is mounted in the physics package and is in optical communication with the quarter wave plate. The vapor cell is located in a second thermal zone that is independent from the first thermal zone. An optical detector is mounted in the physics package and is in optical communication with the vapor cell. The first thermal zone provides a first operation temperature at a first stability point associated with the laser die, and the second thermal zone provides a second operation temperature at a second stability point associated with the vapor cell.
摘要翻译：芯片级原子钟包括物理封装和位于物理封装的第一热区中的激光裸片。四分之一波片安装在物理封装中并与激光裸片光学通信。蒸气室安装在物理封装中并与四分之一波片光学通信。蒸汽池位于独立于第一热区的第二热区中。光学检测器安装在物理封装中并与蒸汽池光学连通。第一热区域在与激光管芯相关联的第一稳定点处提供第一操作温度，并且第二热区域在与蒸汽池相关联的第二稳定点处提供第二操作温度。

4. 发明申请

US20110187466A1 CHIP-SCALE ATOMIC CLOCK WITH TWO THERMAL ZONES 有权
标题翻译：具有两个热区的CHIP-SCALE原子钟
公开(公告)号：US20110187466A1
公开(公告)日：2011-08-04
申请号：US12891441
申请日：2010-09-27
申请人： Daniel W. Youngner , Jeff A. Ridley , Mary K. Salit , Son T. Lu
发明人： Daniel W. Youngner , Jeff A. Ridley , Mary K. Salit , Son T. Lu
IPC分类号： H03B17/00
CPC分类号： G04F5/145 , H01S5/005 , H01S5/02 , H01S5/02208 , H01S5/02296 , H01S5/02453 , H01S5/02476 , H01S5/183
摘要： A chip-scale atomic clock comprises a physics package and a laser die located in a first thermal zone of the physics package. A quarter wave plate is mounted in the physics package and is in optical communication with the laser die. A vapor cell is mounted in the physics package and is in optical communication with the quarter wave plate. The vapor cell is located in a second thermal zone that is independent from the first thermal zone. An optical detector is mounted in the physics package and is in optical communication with the vapor cell. The first thermal zone provides a first operation temperature at a first stability point associated with the laser die, and the second thermal zone provides a second operation temperature at a second stability point associated with the vapor cell.
摘要翻译：芯片级原子钟包括物理封装和位于物理封装的第一热区中的激光裸片。四分之一波片安装在物理封装中并与激光裸片光学通信。蒸气室安装在物理封装中并与四分之一波片光学通信。蒸汽池位于独立于第一热区的第二热区中。光学检测器安装在物理封装中并与蒸汽池光学连通。第一热区域在与激光管芯相关联的第一稳定点处提供第一操作温度，并且第二热区域在与蒸汽池相关联的第二稳定点处提供第二操作温度。

5. 发明申请

US20110187465A1 DESIGN AND PROCESSES FOR STABILIZING A VCSEL IN A CHIP-SCALE ATOMIC CLOCK 有权
标题翻译：用于稳定芯片尺寸原子钟中的VCSEL的设计和工艺
公开(公告)号：US20110187465A1
公开(公告)日：2011-08-04
申请号：US12887259
申请日：2010-09-21
申请人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley
发明人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley
IPC分类号： H03B17/00
CPC分类号： G04F5/145 , H01S5/005 , H01S5/02 , H01S5/02208 , H01S5/02296 , H01S5/02453 , H01S5/02476 , H01S5/183 , H01S2301/02 , Y10T29/49579
摘要： A method to construct a chip-scale atomic clock is provided. The method comprises providing a scaffolding for components in a chip-scale atomic clock. The components include a laser and at least one other component. The method also includes operationally positioning the components on the scaffolding so that an emitting surface of the laser is non-parallel to partially reflective surfaces of the at least one other component.
摘要翻译：提供了一种构建芯片级原子钟的方法。该方法包括为芯片级原子钟中的组件提供脚手架。组件包括激光器和至少一个其它部件。该方法还包括将组件可操作地定位在脚手架上，使得激光的发射表面不平行于至少一个其它组件的部分反射表面。

6. 发明授权

US09146540B2 Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells 有权
标题翻译：制造技术，以提高阳极结合蒸气细胞的压力均匀性
公开(公告)号：US09146540B2
公开(公告)日：2015-09-29
申请号：US13570363
申请日：2012-08-09
申请人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
发明人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
IPC分类号： H01L31/02 , G04F5/14
CPC分类号： G04F5/14 , Y10T428/24149
摘要： A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.
摘要翻译：一种制造蒸汽池的方法包括在具有内表面区域和周边的第一晶片中形成多个蒸汽池模具，并在第一晶片中形成多个互连的排气通道。通气通道为来自每个蒸汽池模具的气体提供至少一个通路，以便在第一晶片的周边外行进。该方法还包括将第二晶片阳极结合到第一晶片的一侧，并将第三晶片阳极结合到第一晶片的相对侧。在第二和第三晶片与第一晶片的阳极接合期间，排气通道允许气体朝向第一晶片的内表面区域与第一晶片的周边外的气体基本上连续的压力平衡。

7. 发明授权

US08242851B2 Processes for stabilizing a VCSEL in a chip-scale atomic clock 有权
标题翻译：用于稳定芯片级原子钟中的VCSEL的过程
公开(公告)号：US08242851B2
公开(公告)日：2012-08-14
申请号：US12887259
申请日：2010-09-21
申请人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley
发明人： Daniel W. Youngner , Son T. Lu , Jeff A. Ridley
IPC分类号： H03B17/00 , H01S1/06
CPC分类号： G04F5/145 , H01S5/005 , H01S5/02 , H01S5/02208 , H01S5/02296 , H01S5/02453 , H01S5/02476 , H01S5/183 , H01S2301/02 , Y10T29/49579
摘要： A method to construct a chip-scale atomic clock is provided. The method comprises providing a scaffolding for components in a chip-scale atomic clock. The components include a laser and at least one other component. The method also includes operationally positioning the components on the scaffolding so that an emitting surface of the laser is non-parallel to partially reflective surfaces of the at least one other component.
摘要翻译：提供了一种构建芯片级原子钟的方法。该方法包括为芯片级原子钟中的组件提供脚手架。组件包括激光器和至少一个其它部件。该方法还包括将组件可操作地定位在脚手架上，使得激光的发射表面不平行于至少一个其它组件的部分反射表面。

8. 发明申请

US20110189429A1 FABRICATION TECHNIQUES TO ENHANCE PRESSURE UNIFORMITY IN ANODICALLY BONDED VAPOR CELLS 有权
标题翻译：制造技术提高阳极粘结蒸汽电池的压力均匀性
公开(公告)号：US20110189429A1
公开(公告)日：2011-08-04
申请号：US12879394
申请日：2010-09-10
申请人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
发明人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
IPC分类号： B32B3/20 , B32B37/02 , B32B37/06 , B32B3/12
CPC分类号： G04F5/14 , Y10T428/24149
摘要： A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.
摘要翻译：一种制造蒸汽池的方法包括在具有内表面区域和周边的第一晶片中形成多个蒸汽池模具，并在第一晶片中形成多个互连的排气通道。通气通道为来自每个蒸汽池模具的气体提供至少一个通路，以便在第一晶片的周边外行进。该方法还包括将第二晶片阳极结合到第一晶片的一侧，并将第三晶片阳极结合到第一晶片的相对侧。在第二和第三晶片与第一晶片的阳极接合期间，排气通道允许气体朝向第一晶片的内表面区域与第一晶片的周边外的气体基本上连续的压力平衡。

9. 发明申请

US20120298295A1 FABRICATION TECHNIQUES TO ENHANCE PRESSURE UNIFORMITY IN ANODICALLY BONDED VAPOR CELLS 有权
标题翻译：制造技术提高阳极粘结蒸汽电池的压力均匀性
公开(公告)号：US20120298295A1
公开(公告)日：2012-11-29
申请号：US13570363
申请日：2012-08-09
申请人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
发明人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
IPC分类号： B32B37/14
CPC分类号： G04F5/14 , Y10T428/24149
摘要： A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.
摘要翻译：一种制造蒸汽池的方法包括在具有内表面区域和周边的第一晶片中形成多个蒸汽池模具，并在第一晶片中形成多个互连的排气通道。通气通道为来自每个蒸汽池模具的气体提供至少一个通路，以便在第一晶片的周边外行进。该方法还包括将第二晶片阳极结合到第一晶片的一侧，并将第三晶片阳极结合到第一晶片的相对侧。在第二和第三晶片与第一晶片的阳极接合期间，排气通道允许气体朝向第一晶片的内表面区域与第一晶片的周边外的气体基本上连续的压力平衡。

10. 发明授权

US08299860B2 Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells 有权
标题翻译：制造技术，以提高阳极结合蒸气细胞的压力均匀性
公开(公告)号：US08299860B2
公开(公告)日：2012-10-30
申请号：US12879394
申请日：2010-09-10
申请人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
发明人： Daniel W. Youngner , Jeff A. Ridley , Son T. Lu
IPC分类号： H01S1/06 , H01L21/30
CPC分类号： G04F5/14 , Y10T428/24149
摘要： A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.
摘要翻译：一种制造蒸汽池的方法包括在具有内表面区域和周边的第一晶片中形成多个蒸汽池模具，并在第一晶片中形成多个互连的排气通道。通气通道为来自每个蒸汽池模具的气体提供至少一个通路，以便在第一晶片的周边外行进。该方法还包括将第二晶片阳极结合到第一晶片的一侧，并将第三晶片阳极结合到第一晶片的相对侧。在第二和第三晶片与第一晶片的阳极接合期间，排气通道允许气体朝向第一晶片的内表面区域与第一晶片的周边外的气体基本上连续的压力平衡。

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