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1. 发明授权

US06577687B2 Method for transmitting data over a data bus with minimized digital inter-symbol interference 失效
标题翻译：通过数字总线以最小的数字符号间干扰传输数据的方法
公开(公告)号：US06577687B2
公开(公告)日：2003-06-10
申请号：US09220089
申请日：1998-12-23
申请人： Dana Hall , Bruce Leshay
发明人： Dana Hall , Bruce Leshay
IPC分类号： G04F1300
CPC分类号： G06F13/4072
摘要： A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the data bus. A pause time is enabled after the data bus has been idle or paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the data bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.
摘要翻译：一种通过数据总线以最小化的数字控制和数据符号间干扰传输数据的方法。数据总线上的电压电平不允许达到由总线终端电压设置的静态负值。为数据检测电路提供额外的时间来检测通过数据总线传送的数据的第一段。在数据总线空闲或暂停长时间后，暂停时间将被启动。在第一段数据被传送之后，该方法通过暂停数据检测电路的正常时间来检测通过数据总线传送的数据的后续段，从而返回正常操作。另外，在具有不变数据位的长时间同步数据传输期间，数据总线被反相并被驱动以进一步调节数据总线电压。

2. 发明授权

US06904479B2 Method for transmitting data over a data bus with minimized digital inter-symbol interference 有权
标题翻译：通过数字总线以最小的数字符号间干扰传输数据的方法
公开(公告)号：US06904479B2
公开(公告)日：2005-06-07
申请号：US10440953
申请日：2003-05-19
申请人： Dana Hall , Bruce Leshay
发明人： Dana Hall , Bruce Leshay
IPC分类号： H04L29/08 , G06F13/40 , G04F13/00
CPC分类号： G06F13/4072
摘要： A method for transmitting data over a data bus with minimized digital control and data inter-symbol interference. The voltage level on the data bus is not permitted to reach the quiescent negated voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the data bus. A pause time is enabled after the data bus has been idle or paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the data bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.
摘要翻译：一种通过数据总线以最小化的数字控制和数据符号间干扰传输数据的方法。数据总线上的电压电平不允许达到由总线终端电压设置的静态负值。为数据检测电路提供额外的时间来检测通过数据总线传送的数据的第一段。在数据总线空闲或暂停长时间后，暂停时间将被启动。在第一段数据被传送之后，该方法通过暂停数据检测电路的正常时间来检测通过数据总线传送的数据的后续段，从而返回正常操作。另外，在具有不变数据位的长时间同步数据传输期间，数据总线被反相并被驱动以进一步调节数据总线电压。

3. 发明授权

US06438159B1 Method and apparatus for margining error rate of multi-drop data buses 失效
标题翻译：多点数据总线误差率保证误差的方法和装置
公开(公告)号：US06438159B1
公开(公告)日：2002-08-20
申请号：US09250978
申请日：1999-02-16
申请人： Richard Uber , Bruce Leshay
发明人： Richard Uber , Bruce Leshay
IPC分类号： H04B1700
CPC分类号： G06F13/423 , G06F13/4086 , G11C29/02
摘要： Method and apparatus for optimizing data transfer over a terminated low voltage differential bus includes controlling parameters of a bus driver, a bus bias cancellation circuit, and other bus operating parameters, in response to received test results derived from test patterns sent over the bus at various transfer rates and parameter settings until optimized parameter settings within an acceptable error margin and at a highest available transfer rate are determined between a particular sending unit and a particular receiving unit on the bus.
摘要翻译：用于优化端接的低电压差分总线上的数据传输的方法和装置包括响应于通过总线发送的测试模式得到的接收测试结果控制总线驱动器的参数，总线偏置消除电路和其他总线工作参数传输速率和参数设置，直到在可接受的错误余量和最高可用传输速率下的优化参数设置在总线上的特定发送单元和特定接收单元之间确定。

4. 发明授权

US5036408A High efficiency disk format and synchronization system 失效
标题翻译：高效磁盘格式和同步系统
公开(公告)号：US5036408A
公开(公告)日：1991-07-30
申请号：US193090
申请日：1988-05-12
申请人： Michael D. Leis , Bruce Leshay , Michael Muchnik , Satish Rege , Charles M. Riggle , Lih-Jyh Weng
发明人： Michael D. Leis , Bruce Leshay , Michael Muchnik , Satish Rege , Charles M. Riggle , Lih-Jyh Weng
IPC分类号： G11B20/10 , G11B5/596 , G11B20/12 , G11B20/14 , G11B27/30
CPC分类号： G11B27/3027 , G11B20/1217 , G11B5/59633 , G11B2020/1282 , G11B2220/20
摘要： A disk drive system provides all required synchronization, positioning, validation, and data functions within each disk sector. All of these functions are provided within two zones, a header section and a data section. The header section includes a preamble, a synchronization character and an address field, as well as servo information for track following. The data section of each sector includes a data preamble, a data synchronization character, a bad sector bit map, the data and data redundancy information. The header section of at least one sector in a track includes a short DC-erase field, a transitionless segment which is used in synchronization. To synchronize a read/write head to the disk, the system first detects the DC-erase field. The system next searches for the header premable and synchronization character. If it finds them within predetermined times, it then looks for a valid sector address to complete the synchronization. If the system does not detect the preamble and synchronization character within the predetermined times, it looks for another DC-erase field and continues the synchronization process. After the preamble and synchronization character are found, the desired sector is located by reading the addresses of the succeeding sectors.

5. 发明授权

US5528607A Method and apparatus for protecting data from mis-synchronization errors 失效
标题翻译：用于保护数据免于错误同步错误的方法和装置
公开(公告)号：US5528607A
公开(公告)日：1996-06-18
申请号：US383201
申请日：1995-02-02
申请人： Lih-Jyh Weng , Bruce Leshay , Diana Langer
发明人： Lih-Jyh Weng , Bruce Leshay , Diana Langer
IPC分类号： G11B20/18 , H03M13/33 , H03M13/00
CPC分类号： H03M13/33 , G11B20/1833
摘要： An encoder in a data processing system generates, from a single m-bit coset leader constant, or symbol, a coset leader, which is a series of k m-bit symbols that resembles a random sequence of km bits. The encoder encodes the m-bit initial coset leader constant in a linear feedback shift register that is characterized by a maximum length polynomial over GF(2). The constants are produced by the register at the same times as the error correction symbols are produced by the encoder. The corresponding constants and symbols are then XOR'd together before the symbols are concatenated with the data symbols to form a code word for recording. A decoder similarly generates the coset leader from the initial constant. The decoder XOR's these constants with the error correction symbols in a retrieved code word as part of a demodulation operation. If the head was in synchronism with the stored information during a read operation, XOR'ing the k coset leader constants with the error correction symbols of the retrieved code word removes the coset leader from these symbols, and thus, reproduces the original error correction symbols. Otherwise, the XOR operation combines the coset leader with a shifted version of itself and introduces into the retrieved code word a number of errors that exceeds the error correction capability of the error correction code used to encode the data. In the preferred embodiment, the linear feedback shift register is characterized by the maximum length polynomial X.sup.9 +X.sup.8 +X.sup.7 +X.sup.3 +X.sup.2 +1 over GF(2), and the m-bit initial coset leader constant is 100001011.
摘要翻译：数据处理系统中的编码器从单个m位陪集前导常量或符号生成陪集首领，该陪集首领是类似于km比特的随机序列的一系列k个m比特符号。编码器对在GF（2）上的最大长度多项式表征的线性反馈移位寄存器中的m位初始陪集前导常数进行编码。常数由寄存器在与编码器产生的纠错符号相同的时间产生。在符号与数据符号连接之前，对应的常数和符号在一起XOR'd以形成用于记录的码字。解码器类似地从初始常数生成陪集前导。解码器XOR的这些常数与检索的码字中的纠错符号作为解调操作的一部分。如果在读取操作期间头部与存储的信息同步，则使用所检索的代码字的纠错符号对k陪集前导符常数进行异或，从这些符号中移除陪集前导符，从而再现原始错误校正符号。否则，XOR操作将陪集前导码与其自身的移位版本相结合，并将检索到的码字引入超过用于对数据进行编码的纠错码的纠错能力的多个错误。在优选实施例中，线性反馈移位寄存器的特征在于GF（2）上的最大长度多项式X9 + X8 + X7 + X3 + X2 + 1，并且m位初始陪集引导常数为100001011。

6. 发明授权

US06553505B1 Method and apparatus for performing clock timing de-skew 有权
标题翻译：用于执行时钟定时去偏移的方法和装置
公开(公告)号：US06553505B1
公开(公告)日：2003-04-22
申请号：US09515462
申请日：2000-02-29
申请人： Russell W. Brown , Bruce Leshay , Mehran Aliahmad
发明人： Russell W. Brown , Bruce Leshay , Mehran Aliahmad
IPC分类号： G06F104
CPC分类号： H04L7/046 , H04L7/0008
摘要： An embodiment of the invention provides a method for performing timing de-skew in order to properly receive digital computer information. A sequence of N clock pulses are generated at intervals having phases offset from one another by T/N, where N is at least 2, T is a duration of one bit-cell time, and one cycle of each of the clock phases has a duration of 2T. A test signal is generated at a transmitting portion. The test signal is received, and one of the generated sequences of clock pulses which is aligned with the test signal is identified. The identified one of the generated sequences of clock pulses is used to determine which one of the generated sequences of clock pulses and which polarity to use to receive data.
摘要翻译：本发明的一个实施例提供了一种用于执行定时去偏转以便正确接收数字计算机信息的方法。 N个时钟脉冲的序列以具有相互偏移T / N的相位的间隔产生，其中N至少为2，T是一个位单元时间的持续时间，并且每个时钟相的一个周期具有持续时间2T。在发送部产生测试信号。接收测试信号，并且识别与测试信号对准的生成的时钟脉冲序列之一。所产生的一个时钟脉冲序列用于确定所生成的时钟脉冲序列中的哪一个以及用于接收数据的哪个极性。

7. 发明授权

US06874097B1 Timing skew compensation technique for parallel data channels 失效
标题翻译：并行数据通道的定时偏移补偿技术
公开(公告)号：US06874097B1
公开(公告)日：2005-03-29
申请号：US09870704
申请日：2001-06-01
申请人： Mehran Aliahmad , Russell W Brown , Bruce Leshay
发明人： Mehran Aliahmad , Russell W Brown , Bruce Leshay
IPC分类号： G06F1/10 , G06F1/12 , G06F5/06
CPC分类号： G06F5/06 , G06F1/10 , G06F1/12 , G06F2205/104 , H03K5/133 , H03K5/135 , H03K2005/00058 , H03K2005/00104
摘要： A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in the data bus. The system separately corrects the receive clock duty cycle, and also features independent de-skewing of the rising and falling edges of a data waveform to improve timing accuracy of transmitted signals. The method and apparatus can be used without substantial changes to existing transmission system protocols, and can be implemented on an all-digital integrated circuit.
摘要翻译：一种用于在并行数据传输系统（诸如小型计算机系统接口（SCSI）数据总线）中相对于数据总线中的接收时钟校正数据信号的定时偏移的方法和装置。系统单独校正接收时钟占空比，并且还具有数据波形的上升沿和下降沿的独立去偏移，以提高发送信号的定时精度。该方法和装置可以用于现有传输系统协议的实质性改变，并且可以在全数字集成电路上实现。

8. 发明授权

US5568627A Header verification in a disk drive using sector histories for improved format efficiency 失效
标题翻译：使用扇区历史的磁盘驱动器中的标题验证，以提高格式效率
公开(公告)号：US5568627A
公开(公告)日：1996-10-22
申请号：US223415
申请日：1994-04-05
申请人： Bruce Leshay , Bruce Buch
发明人： Bruce Leshay , Bruce Buch
IPC分类号： G11B20/10 , G11B19/02 , G11B19/04 , G11B20/12 , G11B20/18 , G11B27/10 , G11B27/30 , G06F12/00
CPC分类号： G11B20/1803 , G11B19/02 , G11B19/04 , G11B20/1252 , G11B20/18 , G11B27/3027 , G11B2020/1267 , G11B2220/2516
摘要： A technique for verifying a pre-recorded header in a disk drive uses verification history to protect against errors that can cause verification failure. A head number, sector address, and upper track address (track MSB) are read from the disk and compared with corresponding expected values. The results of the 5 most recent comparisons are saved in three 5-bit memories. During each verification, a programmable selection and comparison circuit selects M of the stored indicators and determines whether at least N of them indicate a match. If so, the corresponding field is declared to be correctly verified, so that subsequent reads or writes to data blocks within the corresponding sector are allowed to proceed.
摘要翻译：用于验证磁盘驱动器中的预先记录的头部的技术使用验证历史来防止可导致验证失败的错误。从磁盘读取头数，扇区地址和高跟踪地址（轨道MSB），并与相应的预期值进行比较。最近5次比较的结果保存在三个5位存储器中。在每个验证期间，可编程选择和比较电路选择M个存储的指示符，并确定其中至少N个是否表示匹配。如果是这样，则相应的字段被声明为正确验证，以便随后对相应扇区内的数据块的读取或写入被允许进行。

9. 发明授权

US5365382A Synchronization to different fields in a storage device 失效
标题翻译：同步到存储设备中的不同字段
公开(公告)号：US5365382A
公开(公告)日：1994-11-15
申请号：US064286
申请日：1993-05-18
申请人： Lih-Jyh Weng , Michael E. Kastner , Bruce Leshay
发明人： Lih-Jyh Weng , Michael E. Kastner , Bruce Leshay
IPC分类号： G11B20/14 , G11B27/30 , G11B5/09
CPC分类号： G11B20/1426 , G11B27/3027
摘要： A method and apparatus for identifying and synchronizing to two different fields in a disk drive employs different synchronization or "sync" patterns to reduce the chances of mis-identifying and false-identifying a field. Two very distinct synchronization patterns have been found that satisfy the d=1, k=7 run-length constraints of a data code used in the disk drive. During operation, one sync pattern is searched for to identify and synchronize to its associated field, then the field itself is read. This procedure is then repeated for the other sync pattern and its associated field. Also, the phase of a preamble preceding each sync character is established, so that the number of comparisons needed to find either sync character is reduced. A sync detector operates on cell pairs, and has a selector that selects which sync pattern to search for. The sync detector also has special features that enable it to find preamble and DC Erase fields in the disk cell stream.
摘要翻译：用于识别和同步到磁盘驱动器中的两个不同字段的方法和装置采用不同的同步或“同步”模式，以减少错误识别和伪识别字段的机会。已经发现两种非常不同的同步模式满足磁盘驱动器中使用的数据码的d = 1，k = 7游程长度限制。在操作期间，搜索一个同步模式以识别并同步到其相关联的字段，然后读取字段本身。然后对其他同步模式及其相关字段重复该过程。此外，在每个同步字符之前的前导码的相位被建立，使得找到同步字符所需的比较的数量减少。同步检测器对单元对进行操作，并且具有选择器来选择要搜索的同步模式。同步检测器还具有使其能够在磁盘单元流中找到前导码和直流擦除字段的特殊功能。

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