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1. 发明授权

US5065053A Exponential function circuitry 失效
标题翻译：特殊功能电路
公开(公告)号：US5065053A
公开(公告)日：1991-11-12
申请号：US485059
申请日：1990-02-26
申请人： Ivan T. Chan , Russell W. Brown
发明人： Ivan T. Chan , Russell W. Brown
IPC分类号： G06G7/24
CPC分类号： G06G7/24
摘要： Circuitry and method for generating electrical currents representative of an exponential function of an input current. The circuit includes an input diode chain and an output diode chain. Each of the diodes in the input diode chain has an input current passing therethrough. The input current is produced by an input current source connected in sources with the diode below the cathode of the diode. A voltage driving circuit drives a voltage drop across the output diode chain that has a predetermined relationship to the voltage drop across the input diode chain. The voltage drop across the output diode chain results in a current through the output diode chain. The number of diodes in the output diode chain is preselected relative to the number of diodes in the input diode chain such that the current through the output diode chain is representative of an exponential function of the input current or currents.

2. 发明授权

US06553505B1 Method and apparatus for performing clock timing de-skew 有权
标题翻译：用于执行时钟定时去偏移的方法和装置
公开(公告)号：US06553505B1
公开(公告)日：2003-04-22
申请号：US09515462
申请日：2000-02-29
申请人： Russell W. Brown , Bruce Leshay , Mehran Aliahmad
发明人： Russell W. Brown , Bruce Leshay , Mehran Aliahmad
IPC分类号： G06F104
CPC分类号： H04L7/046 , H04L7/0008
摘要： An embodiment of the invention provides a method for performing timing de-skew in order to properly receive digital computer information. A sequence of N clock pulses are generated at intervals having phases offset from one another by T/N, where N is at least 2, T is a duration of one bit-cell time, and one cycle of each of the clock phases has a duration of 2T. A test signal is generated at a transmitting portion. The test signal is received, and one of the generated sequences of clock pulses which is aligned with the test signal is identified. The identified one of the generated sequences of clock pulses is used to determine which one of the generated sequences of clock pulses and which polarity to use to receive data.
摘要翻译：本发明的一个实施例提供了一种用于执行定时去偏转以便正确接收数字计算机信息的方法。 N个时钟脉冲的序列以具有相互偏移T / N的相位的间隔产生，其中N至少为2，T是一个位单元时间的持续时间，并且每个时钟相的一个周期具有持续时间2T。在发送部产生测试信号。接收测试信号，并且识别与测试信号对准的生成的时钟脉冲序列之一。所产生的一个时钟脉冲序列用于确定所生成的时钟脉冲序列中的哪一个以及用于接收数据的哪个极性。

3. 发明授权

US06291980B1 High-resolution measurement of phase shifts in high frequency phase modulators 有权
标题翻译：高频相位调制器相移的高分辨率测量
公开(公告)号：US06291980B1
公开(公告)日：2001-09-18
申请号：US09418212
申请日：1999-10-13
申请人： Mehran Aliahmad , Russell W. Brown
发明人： Mehran Aliahmad , Russell W. Brown
IPC分类号： G01R2500
CPC分类号： G01R15/202
摘要： A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.
摘要翻译：与占空比电路的相位差将相移信号和参考信号转换为具有作为两个信号之间的相位差的函数的占空比的单个信号。在发送到外部测量电路之前，单个信号可以进一步转换为单个直流（DC）值。外部测量电路通过简单地测量直流信号的大小，可以确定相移信号和参考信号之间的相位差。在替代实施例中，基于移位的目标比特模式的直流电压值的测量来确定比特模式的目标比特中的相移，第一比特模式的直流电压值包括表示一个目标位的零相移，以及包括表示目标位的100％相移的非移位位模式的位模式的DC电压值。

4. 发明授权

US5452325A Averaging zero phase start for phase locked loops 失效
标题翻译：锁相环的零相启动平均
公开(公告)号：US5452325A
公开(公告)日：1995-09-19
申请号：US90378
申请日：1993-07-12
申请人： Russell W. Brown , Toai A. Doan , Edward L. Henderson
发明人： Russell W. Brown , Toai A. Doan , Edward L. Henderson
IPC分类号： G11B20/14 , H03L7/10 , H03L7/14 , G11B5/09 , H03D3/24 , H03K5/00 , H03K5/13
CPC分类号： G11B20/1403 , H03L7/10 , H03L7/143
摘要： A phase locked loop has an average zero phase start circuit to detect and correct for the average phase difference between a data signal and a VCO clock signal over a short interval at the beginning of phase-lock acquisition. The average zero phase start circuit has a data comparator to split the data stream into odd and even portions; odd and even pulse position detectors to detect the phase difference between pulses of the odd and even data signals and corresponding pulses of the VCO clock; and a ramp generator to generate a voltage corresponding to the sum of the detected phase differences. The ramp generator employs a capacitor and switched current sources that discharge the capacitor at a fixed rate to generate the voltage. After 4 phase difference measurements are taken, the VCO is stopped, and another current source discharges the capacitor at 4 times the fixed rate. A ramp comparator indicates when the capacitor voltage converges with a reference voltage to restart the VCO in the desired phase alignment with the data signal.
摘要翻译：锁相环具有平均零相启动电路，用于在锁相采集开始时在短时间间隔内检测和校正数据信号与VCO时钟信号之间的平均相位差。平均零相启动电路具有数据比较器，用于将数据流分成奇数和偶数部分; 奇数和偶数脉冲位置检测器，以检测奇数和偶数数据信号的脉冲与VCO时钟的相应脉冲之间的相位差; 以及斜坡发生器，用于产生与所检测的相位差的和相对应的电压。斜坡发生器采用电容器和开关电流源，以固定的速率对电容器放电以产生电压。在进行4个相位差测量之后，VCO停止，另一个电流源以固定速率的4倍放电电容。斜坡比较器指示电容器电压何时与参考电压收敛，以与数据信号期望的相位对准重新启动VCO。

5. 发明授权

US5121085A Dual-charge-pump bandwidth-switched phase-locked loop 失效
标题翻译：双电荷泵带宽开关锁相环
公开(公告)号：US5121085A
公开(公告)日：1992-06-09
申请号：US722752
申请日：1991-06-28
申请人： Russell W. Brown
发明人： Russell W. Brown
IPC分类号： G11B20/14 , H03L7/089 , H03L7/107
CPC分类号： H03L7/0896 , H03L7/0893 , H03L7/0898 , H03L7/107 , G11B20/1403 , H03L2207/04
摘要： Separate charge pumps (58, 60 and 74, 76) drive integral and proportional control paths for a voltage-controlled oscillator (52) in a phase-locked loop (50). A control circuit (74) varies the loop gain of the phase-locked loop by varying the current supplied by the integral-path charge pump (58,60) through a range that is the square of the range through which the current supplied by the proportional-path charge pump (74, 76) is varied. As a consequence, the damping factor of the loop response changes very little as the loop gain is varied through a large range.
摘要翻译：单独的电荷泵（58,60和74,76）驱动锁相环（50）中的压控振荡器（52）的积分和比例控制路径。控制电路（74）通过改变由积分路径电荷泵（58,60）提供的电流通过一个范围的范围来改变锁相环的环路增益，该范围是由比例路径电荷泵（74,76）变化。因此，环路响应的阻尼因子随着环路增益在大范围内变化而变化很小。

6. 发明申请

US20140072264A1 DELIVERY OF GPON TECHNOLOGY 有权
标题翻译：交付GPON技术
公开(公告)号：US20140072264A1
公开(公告)日：2014-03-13
申请号：US13608156
申请日：2012-09-10
申请人： Richard Schroder , Russell W. Brown , Thomas C. Ruvarac , John Silovich , Andrew G. Low
发明人： Richard Schroder , Russell W. Brown , Thomas C. Ruvarac , John Silovich , Andrew G. Low
IPC分类号： G02B6/36
CPC分类号： H04J14/00
摘要： A wall-mountable outlet comprising an enclosure and a faceplate mechanically coupled to the enclosure. An optical network terminal (ONT) is provided in the enclosure. In one example embodiment, the ONT comprises an optical-electrical (O-E) data module, and the O-E data module comprises an O-E converter. The O-E data module can further comprise a switch arranged to selectively couple at least one signal with the O-E converter. The O-E data module further can comprise a Passive Optical Network (PON) controller interposed between the O-E converter and the switch.
摘要翻译：一种壁挂式出口，其包括机壳连接到外壳的外壳和面板。光纤网络终端（ONT）设在机箱内。在一个示例实施例中，ONT包括光电（O-E）数据模块，O-E数据模块包括O-E转换器。 O-E数据模块还可以包括被配置为选择性地将至少一个信号与O-E转换器耦合的开关。 O-E数据模块还可以包括插入在O-E转换器和开关之间的被动光网络（PON）控制器。

7. 发明授权

US06794920B1 Sampled analog DC offset correction for data bus structures 失效
标题翻译：数据总线结构的采样模拟直流偏移校正
公开(公告)号：US06794920B1
公开(公告)日：2004-09-21
申请号：US09569036
申请日：2000-05-11
申请人： Mehran Aliahmad , Kristopher Kshonze , Russell W. Brown
发明人： Mehran Aliahmad , Kristopher Kshonze , Russell W. Brown
IPC分类号： H03K508
CPC分类号： H04L25/063 , H03K5/003 , H03K5/08
摘要： A circuit for measuring and compensating for DC offset introduced into a differential signal due to, for example, terminator mismatches and interconnect resistance, is described herein. The circuit includes a plurality of capacitors that store test values of a differential signal, a summer, a comparator, a digital counter, and an analog-to-digital converter. The summer sums signals from the plurality of capacitors and a dc offset correction signal from the analog-to-digital converter. A differential output from the summer is processed by the comparator to generate a binary output signal that is used to recursively modify the value of the dc offset correction signal until the dc offset correction signal stabilizes.
摘要翻译：本文描述了用于测量和补偿由于例如终端错误和互连电阻引入到差分信号中的DC偏移的电路。该电路包括存储差分信号，加法器，比较器，数字计数器和模数转换器的测试值的多个电容器。夏季对来自多个电容器的信号和来自模拟 - 数字转换器的直流偏移校正信号进行求和。比较器处理来自加法器的差分输出，以产生二进制输出信号，用于递归地修改直流偏移校正信号的值，直到直流偏移校正信号稳定。

8. 发明授权

US06642868B1 Apparatus and method for the correction of DC offset in data bus structures at the receiver 失效
标题翻译：用于在接收机处校正数据总线结构中的直流偏移的装置和方法
公开(公告)号：US06642868B1
公开(公告)日：2003-11-04
申请号：US10051137
申请日：2002-01-22
申请人： Russell W. Brown , Kristopher Kshonze , Ivan Chan , Mehran Aliahmad
发明人： Russell W. Brown , Kristopher Kshonze , Ivan Chan , Mehran Aliahmad
IPC分类号： H03M110
CPC分类号： H03M1/1295 , H03M1/1019 , H03M1/12
摘要： DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for in another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.
摘要翻译：引入到差分信号的DC偏移由DC偏移校正电路补偿。 DC偏移校正电路接收交替逻辑高电平和逻辑低电平（即10101010等）的已知训练模式。在一个实施例中，所接收的信号被积分，并且结果与预定的参考电平相比较。比较结果用于调整附加到接收信号的DC偏移校正值。迭代地执行该过程，直到比较的连续结果指示在另一个实施例中已经补偿了DC偏移，则计算接收信号的占空比。使用占空比计算的结果来迭代地调整DC偏移校正值。

9. 发明申请

US20120251097A1 PASSIVE ARCHITECTURAL OPTICAL DISTRIBUTION NETWORK 审中-公开
标题翻译：被动建筑光学分布网络
公开(公告)号：US20120251097A1
公开(公告)日：2012-10-04
申请号：US13177081
申请日：2011-07-06
申请人： Ahmad Elmardini , Russell W. Brown
发明人： Ahmad Elmardini , Russell W. Brown
IPC分类号： H04B10/08
CPC分类号： H04B10/032 , H04B10/079
摘要： Passive optical networks can experience faults that are unrecoverable. An embodiments of the present invention is a hybrid passive optical network configured to protect a primary optical path employing a switch to transmit data from the primary path to a secondary path in a passive manner. In an event data flows through both the primary path and the secondary path, the optical switch may be configured to monitor the primary path. In such an embodiment, the optical switch is a protection optical switch that is sensitive to monitoring an optical signal that flows on the primary path. If the switch detects a loss of signal on the primary path, the optical switch automatically switches delivery of the optical signal from the primary path to the secondary path, via the optical switch to allow an optical line terminal to receive optical signals virtually uninterrupted.
摘要翻译：被动光网络可能会遇到不可恢复的故障。本发明的实施例是被配置为保护采用交换机的主光路以被动方式将数据从主路径传输到次路径的混合无源光网络。在数据流经主路径和次路径的事件中，光开关可以被配置为监视主路径。在这样的实施例中，光开关是对监视在主路径上流动的光信号敏感的保护光开关。如果开关检测到主路径上的信号丢失，则光开关通过光开关自动切换光信号从主路径到次路径的传送，以允许光线路终端几乎不间断地接收光信号。

10. 发明授权

US06724839B1 Adaptive inter-symbol interference boost equalization apparatus and method 有权
标题翻译：自适应符号间干扰提升均衡装置及方法
公开(公告)号：US06724839B1
公开(公告)日：2004-04-20
申请号：US09514572
申请日：2000-02-28
申请人： Ivan Chan , Russell W. Brown , Mehran Aliahmad
发明人： Ivan Chan , Russell W. Brown , Mehran Aliahmad
IPC分类号： H03D104
CPC分类号： H04L25/14 , H04L25/03159 , H04L2025/03356 , H04L2025/03522
摘要： An apparatus mitigates inter-symbol interference effects on an oscillating signal from which digital data will be obtained at a receive end of a channel. The inter-symbol interference is introduced into the oscillating signal as a result of transmitting the oscillating signal through the transmission channel over a substantial distance from a transmit device to the receive end of the channel. A filter element receives an input signal from the transmit device and outputs a filtered signal within a predetermined frequency band. The filter element has a mechanism for adjusting a gain for a given range of frequencies within the predetermined frequency band. The given range of frequencies corresponds to higher frequencies in the predetermined frequency band. An amplitude determining mechanism determines a peak amplitude of the filtered signal. A boost gain control mechanism controls adjustments to the high frequency gain so that the peak-to-peak amplitude of the filtered signal is maintained within a predetermined amplitude range.
摘要翻译：一种装置减轻了在通道的接收端将获得数字数据的振荡信号上的符号间干扰效应。作为通过传输信道在从传输设备到信道的接收端的实际距离上传送振荡信号的结果，将符号间干扰引入到振荡信号中。滤波器元件接收来自发送装置的输入信号，并输出预定频带内的滤波信号。滤波器元件具有用于调整在预定频带内的给定频率范围内的增益的机构。给定的频率范围对应于预定频带中的较高频率。幅度确定机构确定滤波信号的峰值幅度。升压增益控制机构控制对高频增益的调整，使得滤波信号的峰 - 峰幅度保持在预定幅度范围内。

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