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1. 发明专利

JP2012204653A Semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012204653A
公开(公告)日：2012-10-22
申请号：JP2011068505
申请日：2011-03-25
申请人： Dainippon Printing Co Ltd , Shinko Electric Ind Co Ltd , Nec Corp , Toppan Printing Co Ltd , Ibiden Co Ltd , National Institute Of Advanced Industrial & Technology , イビデン株式会社 , 凸版印刷株式会社 , 大日本印刷株式会社 , 新光電気工業株式会社 , 日本電気株式会社 , 独立行政法人産業技術総合研究所
发明人： SHIMADA OSAMU , TAKEUCHI YUKIHARU , GOMYO TOSHIO , BABA KAZUHIRO , TAKEMURA KOICHI , OKUBO RIICHI , SHIMAKURA KEI , SAKAI ATSUSHI , AOYANAGI MASAHIRO , KIKUCHI KATSUYA
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a structure capable of improving connection reliability between a semiconductor chip and an intermediary substrate and of reducing cost, in a semiconductor device configured by laminating a plurality of semiconductor chips and having an external connection terminal on the intermediary substrate.SOLUTION: A semiconductor device has: a first semiconductor chip having a first through electrode group; a laminated second semiconductor chip having a second through electrode group and a connection terminal group, which is opposed to the first through electrode group of a rear face side of the first semiconductor chip to establish electrical conduction with the first through electrode group; a third semiconductor chip having a connection terminal group, a third through electrode group, a re-wiring layer 44 provided on a surface on an opposite side to the connection terminal group, and an anti-intermediary substrate connection terminal 61 group formed on the surface where the re-wiring layer 44 is present so as to have electrical conduction with the re-wiring layer 44 and having the minimum pitch of arrangement longer than that of the second through electrode group; and a laminated intermediary substrate 100.
摘要翻译：要解决的问题：为了提供能够提高半导体芯片和中间基板之间的连接可靠性并降低成本的结构，在通过层叠多个半导体芯片并且在其上具有外部连接端子的半导体器件中中间底物。解决方案：半导体器件具有：具有第一贯通电极组的第一半导体芯片; 具有第二通电极组和连接端子组的层叠的第二半导体芯片，与第一半导体芯片的背面侧的第一贯通电极组相对，以与第一贯通电极组建立导电; 具有连接端子组的第三半导体芯片，设置在与连接端子组相反的一侧的表面上的再配线层44以及在该表面上形成的反中介基板连接端子61组的第三贯通电极组，再配线层44 其中重新布线层44存在，以便与再布线层44导通，并且具有比第二通孔电极组更短的布置的最小间距; 和层压的中间衬底100.版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2009170941A Capacitor mounting wiring board 有权
标题翻译：电容安装接线板
公开(公告)号：JP2009170941A
公开(公告)日：2009-07-30
申请号：JP2009112185
申请日：2009-05-01
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： HARUHARA MASAHIRO , MURAYAMA HIROSHI , HIGASHI MITSUTOSHI , GOMYO TOSHIO , TAKEUCHI YUKIHARU
IPC分类号： H05K3/46 , H01L23/12 , H01L25/00
CPC分类号： H01L2224/16 , H01L2224/16235 , H01L2924/15311 , H01L2924/19105
摘要： PROBLEM TO BE SOLVED: To contribute to improvement in operation reliability of a mounted semiconductor element etc., by reducing ESL of a mounted capacitor and performing effective decoupling. SOLUTION: On the capacitor mounting wiring board 10b, a plurality of wiring layers 14a and 14b, 16a and 16b, and 18a and 18b patterned in necessary shapes respectively are laminated with insulating layers 15a and 15b, and 17a and 17b interposed, and connected to each other through conductors formed penetrating the insulating layers along the thicknesses. A capacitor 1 for decoupling is electrically connected to the wiring layers in vicinity to the wiring layer 18a as the outermost layer provided as a power line or ground line, and surface-mounted such that when a current flows to the capacitor 1, the direction of the current is opposite to the direction of a current flowing to the wiring layer 18a and a path of the current flowing to the capacitor is substantially parallel to a path of the current flowing to the wiring layer. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过减少安装的电容器的ESL并执行有效的去耦，有助于提高安装的半导体元件的操作可靠性等。解决方案：在电容器安装布线板10b上，分别以必要的形状分别图案化的多个布线层14a和14b，16a和16b以及18a和18b层叠绝缘层15a和15b，并插入17a和17b，并且通过沿着厚度贯穿绝缘层的导体彼此连接。用于去耦的电容器1作为布线层18a附近的布线层电连接，作为设置为电力线或地线的最外层，并且表面安装使得当电流流向电容器1时，电流与流向布线层18a的电流的方向相反，并且流向电容器的电流的路径基本上平行于流向布线层的电流的路径。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2006156636A Mounting structure of semiconductor device and semiconductor device using the same 审中-公开
标题翻译：使用其的半导体器件和半导体器件的安装结构
公开(公告)号：JP2006156636A
公开(公告)日：2006-06-15
申请号：JP2004343797
申请日：2004-11-29
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： TAKEUCHI YUKIHARU , TAKAYANAGI HIDENORI , GOMYO TOSHIO
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in electric characteristics by shortening wiring which connects a semiconductor device and an external connection terminal to the extent of the equal length while securing external connection terminal allocation area.
SOLUTION: The semiconductor device is constituted such that: on the surface, it has a contact button 32 and an external connection terminal 40; on the backside it has a wiring pattern film 30 formed respectively on the wiring pattern electrically connected with the contact button 32; a semiconductor device 50 where a semiconductor device 10 is mounted via the wiring pattern contact buttons 32 are respectively formed in one half part and other half part of a film substrate; the semiconductor device 10 is mounted in one half part of the wiring pattern film, and the other half part is turned up to the backside of the semiconductor device 10 so that the contact buttons 32 may be exposed to both the external surfaces; and on the external surface of the wiring pattern film 30 of the side wall of the semiconductor device 10, an external connection terminal 40 is formed to be connected with the semiconductor device 10 electrically via the wiring pattern provided in the film substrate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决方案：通过缩短将半导体器件和外部连接端子连接到等长的程度的布线来提供具有优异电特性的半导体器件，同时确保外部连接端子分配区域。解决方案：半导体器件构成为：表面上具有触点按钮32和外部连接端子40; 在其背面具有分别形成在与接触按钮32电连接的布线图案上的布线图案膜30; 通过布线图案接触按钮32安装半导体器件10的半导体器件50分别形成在薄膜基板的一个半部分和另一半部分中; 半导体器件10安装在布线图案膜的一半部分中，另一半部分被转到半导体器件10的背面，使得触点按钮32可以暴露于两个外表面; 并且在半导体器件10的侧壁的布线图案膜30的外表面上，形成外部连接端子40，以通过设置在膜基板中的布线图案与半导体器件10电连接。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006005309A Capacitor device 审中-公开
标题翻译：电容器件
公开(公告)号：JP2006005309A
公开(公告)日：2006-01-05
申请号：JP2004182773
申请日：2004-06-21
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： TAKEUCHI YUKIHARU , GOMYO TOSHIO , MIYAMOTO TAKAHARU
IPC分类号： H01G4/38 , H01G2/00 , H01G2/06 , H01G4/12
摘要： PROBLEM TO BE SOLVED: To provide a capacitor device, applicable to a decoupling capacitor adaptable to higher-frequency (1 GHz or higher) applications to electronic components (LSIs).
SOLUTION: The capacitor device has a plurality of coaxial capacitors C aligned in line, each comprising a column-formed electrical conductor 10; a dielectric layer 12 that covers the outer circumferential surface of the column-formed electrical conductor 10; and an outer electrically conductive layer 14 that covers the outer circumferential surface of the dielectric layer 12, wherein a first connection terminal 24 is connected to the outer electrically conductive layers 14 in the plurality of coaxial capacitors C, second connection terminals 26a, 26b are connected to the columnar electrical conductors 10 in the plurality of coaxial capacitors C, and the plurality of coaxial capacitors C are connected electrically in parallel.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供适用于适用于电子部件（LSI）的高频（1GHz或更高）应用的去耦电容器的电容器装置。解决方案：电容器装置具有排列成一行的多个同轴电容器C，每个包括一列柱形电导体10; 覆盖柱状电导体10的外周面的电介质层12; 以及覆盖电介质层12的外周面的外部导电层14，其中第一连接端子24连接到多个同轴电容器C中的外部导电层14，第二连接端子26a，26b连接到多个同轴电容器C中的柱状电导体10，并且多个同轴电容器C并联电连接。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005268533A Laminated semiconductor device 审中-公开
标题翻译：层压半导体器件
公开(公告)号：JP2005268533A
公开(公告)日：2005-09-29
申请号：JP2004078781
申请日：2004-03-18
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： TAKEUCHI YUKIHARU , GOMYO TOSHIO
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2225/06562 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a laminated semiconductor device that is less in structural restriction and can be manufactured at a low cost.
SOLUTION: In the laminated semiconductor device, a first semiconductor chip has a first main surface and a plurality of first pads formed on the first end side of the first main surface, and a second semiconductor chip has a second main surface installed on the first main surface in a shifted state so that the first pads may be exposed, and a plurality of second pads on the second end side of the second main surface separated from the first end side are formed. In the semiconductor device, in addition, a plurality of external connection wiring electrically connected to the first or second pads is formed on the third main surface side on the opposite side of the first main surface. The external connection wiring is formed so that the wiring may be extended in the direction in which the wiring is separated from the first semiconductor chip and at least parts of the first and second pads are electrically connected to each other through the external connection wiring.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供结构限制较少并且可以以低成本制造的层叠半导体器件。解决方案：在层叠半导体器件中，第一半导体芯片具有第一主表面和形成在第一主表面的第一端侧上的多个第一焊盘，第二半导体芯片具有安装在第二主表面上的第二主表面第一主表面处于移位状态，使得第一焊盘可能被暴露，并且形成与第一端侧分离的第二主表面的第二端侧上的多个第二焊盘。另外，在半导体装置中，与第一或第二焊盘电连接的多个外部连接布线形成在第一主表面的相对侧的第三主表面侧上。外部连接布线形成为使得布线可以沿着布线从第一半导体芯片分离的方向延伸，并且第一和第二焊盘的至少一部分通过外部连接布线彼此电连接。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005294383A Capacitor mounting wiring board and manufacturing method thereof 有权
标题翻译：电容安装接线板及其制造方法
公开(公告)号：JP2005294383A
公开(公告)日：2005-10-20
申请号：JP2004104660
申请日：2004-03-31
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： HARUHARA MASAHIRO , MURAYAMA HIROSHI , AZUMA MITSUTOSHI , GOMYO TOSHIO , TAKEUCHI YUKIHARU
IPC分类号： H05K3/46 , H01L21/4763 , H01L23/12 , H01L23/498 , H01L23/50 , H01L25/00 , H05K1/02 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49822 , H01L23/50 , H01L2224/16 , H01L2224/16235 , H01L2224/73204 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/15192 , H01L2924/15311 , H01L2924/19105 , H01L2924/19106 , H05K1/0231 , H05K1/113 , H05K1/185 , H05K3/4602 , H05K2201/0792 , H05K2201/09772 , H05K2201/10636 , Y02P70/611
摘要： PROBLEM TO BE SOLVED: To provide a newly proposed capacitor mounting wiring board and manufacturing method thereof which can make contribution to improvement in operation reliability of semiconductor element or the like to be mounted by effective decoupling through reduction of ESL of the capacitor to be mounted. SOLUTION: In the capacitor mounting wiring board 10e, a plurality of wiring layers 14a, 14b, 16a, 16b, 18a, 18b formed as the patterns of the predetermined shape are laminated via insulating layers 15a, 15b, 17a, and 17b and are mutually connected via a conductor formed through the insulating layers in the thickness direction. The capacitor 1 for decoupling is electrically connected with the relevant wiring layer adjacent to the wiring layers 14a, 18a provided as power supply line or ground line. Moreover, this capacitor 1 is mounted to invert the direction of current flowing into the relevant wiring layers 14a, 18a from that of the current when it is applied to the capacitor 1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种新提出的电容器安装布线板及其制造方法，其可以通过将电容器的ESL的减小有效地去耦以有助于提高半导体元件等的操作可靠性，被安装。解决方案：在电容器安装配线板10e中，通过绝缘层15a，15b，17a和17b层叠形成为预定形状的图案的多个布线层14a，14b，16a，16b，18a，18b 并且经由绝缘层在厚度方向上形成的导体相互连接。用于去耦的电容器1与邻近布线层14a，18a设置的电源线或接地线的相关布线层电连接。此外，该电容器1被安装成在被施加到电容器1时将流过相关布线层14a，18a的电流的方向与电流的方向反转。（C）2006，JPO＆NCIPI

7. 发明专利

JP2005268534A Semiconductor chip and laminated semiconductor device 审中-公开
标题翻译：半导体芯片和层压半导体器件
公开(公告)号：JP2005268534A
公开(公告)日：2005-09-29
申请号：JP2004078782
申请日：2004-03-18
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： TAKEUCHI YUKIHARU , GOMYO TOSHIO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/06 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/06153 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49 , H01L2224/4911 , H01L2224/73265 , H01L2225/06562 , H01L2225/06568 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a laminated semiconductor device that is less in structural restriction and can be manufactured at a low cost, and to provide a semiconductor chip used for the semiconductor device. SOLUTION: The laminated semiconductor device has a first semiconductor chip having first on-chip wiring on its first main surface, a second semiconductor chip laminated upon the first main surface and having second on-chip wiring on its second main surface, and a plurality of external connection wiring electrically connected to the first on-chip or second on-chip wiring. The second on-chip wiring is formed on the second main surface so that the wiring may be extended from the first end side to the second end section side of the main surface and electrically connected to the first on-chip wiring or external connection wiring. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供结构限制较少并且可以以低成本制造的叠层半导体器件，并提供用于半导体器件的半导体芯片。解决方案：层叠半导体器件具有在其第一主表面上具有第一片上布线的第一半导体芯片，层叠在第一主表面上并在其第二主表面上具有第二芯片布线的第二半导体芯片，以及电连接到第一片上或第二片上布线的多个外部连接布线。第二片上布线形成在第二主表面上，使得布线可以从主表面的第一端侧延伸到第二端部侧，并且电连接到第一片上布线或外部连接布线。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2012164877A Lead frame, lead frame manufacturing method, semiconductor device and semiconductor device manufacturing method 有权
标题翻译：引线框架，引线框架制造方法，半导体器件和半导体器件制造方法
公开(公告)号：JP2012164877A
公开(公告)日：2012-08-30
申请号：JP2011025132
申请日：2011-02-08
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： TAKEUCHI YUKIHARU , YOSHIE TAKASHI , OGUSHI MASAYUKI
IPC分类号： H01L23/50
CPC分类号： H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a lead frame, a lead frame manufacturing method, a semiconductor device and a semiconductor device manufacturing method, which can inhibit separation of a resin embedded in an opening.SOLUTION: A lead frame 1 in which a plurality of unit lead frames 10 each having a die pad 13 and leads 14 are connected, comprises: an opening 15 with an internal surface 15A on which a rough surface plating layer 17 roughened on a surface is formed; and an insulating resin layer 18 embedded in the opening 15 so as to contact a roughened surface 17A of the rough surface plating layer 17.
摘要翻译：要解决的问题：提供一种可以抑制嵌入在开口中的树脂的分离的引线框架，引线框架制造方法，半导体器件和半导体器件制造方法。解决方案：其中连接有具有管芯焊盘13和引线14的多个单元引线框架10的引线框架1包括：具有内表面15A的开口15，粗糙表面镀层17在其上粗糙化形成表面; 以及嵌入在开口15中以与粗糙表面镀层17的粗糙表面17A接触的绝缘树脂层18。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2011134956A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011134956A
公开(公告)日：2011-07-07
申请号：JP2009294434
申请日：2009-12-25
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI YOSHIE , FUJII TOMOJI , TAKEUCHI YUKIHARU
IPC分类号： H01L23/40 , H01L21/60 , H01L23/12
CPC分类号： H01L23/3677 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L24/73 , H01L2223/6677 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To shorten wire bonding length placed in high-frequency transmission lines, such as a millimeter wave-band, to prevent deterioration in the signal quality affected by the parasitic inductance of that portion, and to enhance heat dissipation. SOLUTION: A semiconductor device 10 has a structure, where a semiconductor element (chip) 30 is mounted in a cavity 27 formed on a wiring substrate 20, with an adhesive material 33 disposed between the chip and the bottom surface of the cavity, and the electrode terminal 31 of the chip is connected with wiring portions 22a and 22b, formed in the periphery of the cavity on the substrate through a wire 32. The chip 30 is mounted so as to stick to a sidewall 27a of the cavity, near a region where a wiring 22a for high frequencies as compared with other wirings of the wiring portions is formed, and a concave portion 28 is formed at the bottom surface 27e of the cavity on the side to which the chip 30 has been stuck; and further, a thermal via 29, connected from the bottom surface of this concave portion to the outside of the substrate, is arranged. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了缩短放置在诸如毫米波段的高频传输线中的引线接合长度，以防止由该部分的寄生电感影响的信号质量的劣化，并且增强散热。解决方案：半导体器件10具有其中将半导体元件（芯片）30安装在形成在布线基板20上的空腔27中的结构，其中粘合材料33设置在芯片与腔体的底表面之间并且芯片的电极端子31通过线32与形成在基板的空腔的周边的布线部分22a和22b连接。芯片30安装成粘附到空腔的侧壁27a，在与布线部分的其它布线相比形成用于高频的布线22a的区域附近，并且在芯片30已经被卡住的一侧的空腔的底面27e处形成凹部28; 并且还设置有从该凹部的底面到基板的外部连接的热通路29。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2008300854A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008300854A
公开(公告)日：2008-12-11
申请号：JP2008173347
申请日：2008-07-02
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： TAKEUCHI YUKIHARU , TAKAYANAGI HIDENORI
IPC分类号： H05K3/46 , H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18 , H05K1/18
CPC分类号： H01L25/105 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/19 , H01L2225/1035 , H01L2225/1058 , H01L2924/10253 , H01L2924/18162 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To miniaturize a semiconductor device (chip) in mounting the same on a package and contribute to a high functionalization thereof by simply implementing a three-dimensional layout configuration of the chip and interconnection thereof as required and enhancing flexibility in wiring. SOLUTION: In the semiconductor device 10b, via holes VH1 are formed around the chip 30 embedded in the package 20b, one end of a conductor 22b filled in the via hole is exposed outside through a pad section 23b, or is connected to the other end of the conductor 22b to form a wiring layer 24, a pad section 24P corresponding to the conductor 22b of the wiring layer is exposed from a protective film 25, or an external connection terminal 26 is bonded onto the section 24P. An electrode terminal of the chip 30 is connected to the wiring layer 24. Further, one end of the conductor 22b is protruded outside through the section 23b. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了将其安装在封装上的半导体器件（芯片）小型化并且通过简单地实现芯片的三维布局配置和所需的互连并增强灵活性而有助于其高功能化在接线。解决方案：在半导体器件10b中，在嵌入在封装20b中的芯片30周围形成通孔VH1，填充在通孔中的导体22b的一端通过焊盘部23b暴露在外部，或者连接到导体22b的另一端形成布线层24，与布线层的导体22b相对应的焊盘部分24P从保护膜25露出，或外部连接端子26接合到部分24P上。芯片30的电极端子连接到布线层24.此外，导体22b的一端通过部分23b向外突出。版权所有（C）2009，JPO＆INPIT

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