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    • 3. 发明申请
    • SEMICONDUCTOR DEVICE AND RELATED METHOD OF FABRICATION
    • 半导体器件及相关制造方法
    • US20120037995A1
    • 2012-02-16
    • US13175976
    • 2011-07-05
    • Yongdon KimDaeshik Kim
    • Yongdon KimDaeshik Kim
    • H01L27/088
    • H01L29/0847H01L29/41758H01L29/665H01L29/66575H01L29/7833
    • A semiconductor device comprises a device isolation pattern, an active region, a gate pattern, a first source/drain region, and a first barrier region. The device isolation pattern defines an active portion in a semiconductor substrate and the active portion comprises first and second sidewalls extending in a first direction and doped with a first conductive type dopant. The gate pattern extends in a second direction perpendicular to the first direction to cross over the active portion. The first source/drain region and the first barrier region are disposed in the active portion at one side of the gate pattern. The first barrier region is disposed between the first source/drain region and the first sidewall and contacts the first sidewall. The first barrier region is doped with the first conductive type dopant and the first source/drain region is doped with a second conductive type dopant.
    • 半导体器件包括器件隔离图案,有源区,栅极图案,第一源极/漏极区域和第一势垒区域。 器件隔离图案限定半导体衬底中的有源部分,并且有源部分包括在第一方向上延伸并掺杂有第一导电型掺杂剂的第一和第二侧壁。 栅极图案沿垂直于第一方向的第二方向延伸以越过有效部分。 第一源极/漏极区域和第一势垒区域设置在栅极图案的一侧的有源部分中。 第一阻挡区域设置在第一源极/漏极区域和第一侧壁之间并且接触第一侧壁。 第一阻挡区域掺杂有第一导电型掺杂剂,并且第一源极/漏极区域掺杂有第二导电型掺杂剂。
    • 5. 发明授权
    • Semiconductor device and related method of fabrication
    • 半导体器件及相关制造方法
    • US08471339B2
    • 2013-06-25
    • US13175976
    • 2011-07-05
    • Yongdon KimDaeshik Kim
    • Yongdon KimDaeshik Kim
    • H01L21/70
    • H01L29/0847H01L29/41758H01L29/665H01L29/66575H01L29/7833
    • A semiconductor device comprises a device isolation pattern, an active region, a gate pattern, a first source/drain region, and a first barrier region. The device isolation pattern defines an active portion in a semiconductor substrate and the active portion comprises first and second sidewalls extending in a first direction and doped with a first conductive type dopant. The gate pattern extends in a second direction perpendicular to the first direction to cross over the active portion. The first source/drain region and the first barrier region are disposed in the active portion at one side of the gate pattern. The first barrier region is disposed between the first source/drain region and the first sidewall and contacts the first sidewall. The first barrier region is doped with the first conductive type dopant and the first source/drain region is doped with a second conductive type dopant.
    • 半导体器件包括器件隔离图案,有源区,栅极图案,第一源极/漏极区域和第一势垒区域。 器件隔离图案限定半导体衬底中的有源部分,并且有源部分包括在第一方向上延伸并掺杂有第一导电型掺杂剂的第一和第二侧壁。 栅极图案沿垂直于第一方向的第二方向延伸以越过有效部分。 第一源极/漏极区域和第一势垒区域设置在栅极图案的一侧的有源部分中。 第一阻挡区域设置在第一源极/漏极区域和第一侧壁之间并且接触第一侧壁。 第一阻挡区域掺杂有第一导电型掺杂剂,并且第一源极/漏极区域掺杂有第二导电型掺杂剂。