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1. 发明授权

US5673221A Circuit and method for reading a memory cell that can store multiple bits of data 失效
标题翻译：用于读取可存储多个数据位的存储单元的电路和方法
公开(公告)号：US5673221A
公开(公告)日：1997-09-30
申请号：US592939
申请日：1996-01-29
申请人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
IPC分类号： G11C16/04 , G11C11/56 , G11C16/02 , G11C17/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.
摘要翻译：用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流。

2. 再颁专利

USRE38166E1 Circuit and method for reading a memory cell that can store multiple bits of data 有权
标题翻译：用于读取可存储多个数据位的存储单元的电路和方法
公开(公告)号：USRE38166E1
公开(公告)日：2003-07-01
申请号：US09410164
申请日：1999-09-30
申请人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
IPC分类号： G11C1156
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m−2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.
摘要翻译：用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流。

3. 发明授权

US5838612A Reading circuit for multilevel non volatile memory cell devices 失效
标题翻译：多电平非易失性存储单元器件的读取电路
公开(公告)号：US5838612A
公开(公告)日：1998-11-17
申请号：US869072
申请日：1997-06-04
申请人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/06 , G11C11/34
CPC分类号： G11C11/5642 , G11C11/5621 , G11C2211/5631
摘要： Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.
摘要翻译：用于多电平非易失性存储单元器件的读取电路，对于要读取的每个单元，具有与负载和去耦合和控制级相关联的选择线，其具有稳定选择线的电路节点上的电压的反馈环路。对该节点连接由反馈回路控制的当前复制电路。这些包括与与存储器单元的选择线相关的负载和电路元件同源的负载和电路元件，并且具有用于连接到电流比较器电路的输出接口电路。

4. 发明授权

US5729490A Parallel-dichotomic serial sensing method for sensing multiple-level non-volatile memory cells, and sensing circuit for actuating such method 失效
标题翻译：用于感测多级非易失性存储单元的并行二分辨串行感测方法，以及用于启动这种方法的感测电路
公开(公告)号：US5729490A
公开(公告)日：1998-03-17
申请号：US690059
申请日：1996-07-31
申请人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
IPC分类号： G11C11/56 , G11C7/00
CPC分类号： G11C11/5642 , G11C11/5621 , G11C2211/5632 , G11C2211/5633
摘要： A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current with a prescribed number of reference currents having values comprised between a minimum value and a maximum value of said discrete set of m cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current belongs; repeating step (a) for the sub-set of cell current values to which the cell current belongs, until the sub-set of cell current values to which the cell current belongs comprises only one cell current value, which is the value of the current of the memory cell to be sensed.
摘要翻译：用于感测可以在多个m = 2n（n> = Z）个不同编程级别中采取一个编程电平的多级非易失性存储器单元的方法提供了在预定条件下偏置要感测的存储器单元，因此存储器单元以具有m个不同单元电流值的离散集合的值吸收单元电流，每个单元电流值对应于所述编程电平之一。感测方法还提供：同时将电池电流与规定数量的参考电流进行比较，所述规定数量的参考电流具有包括在所述离散的一组m个电池电流值的最小值和最大值之间的值，并且将所述离散的一组m个电池电流值多个子单元电流子集，用于确定单元电流所属的单元电流值的子集; 对于单元电流所属的单元电流值的子集重复步骤（a），直到单元电流所属的单元电流值的子集仅包括一个单元电流值，该单元电流值是电流值的待读取的存储单元。

5. 发明授权

US5694363A Reading circuit for memory cell devices having a low supply voltage 失效
标题翻译：具有低电源电压的存储单元器件的读取电路
公开(公告)号：US5694363A
公开(公告)日：1997-12-02
申请号：US638976
申请日：1996-04-25
申请人： Cristiano Calligaro , Roberto Gastaldi , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Roberto Gastaldi , Nicola Telecco , Guido Torelli
IPC分类号： G11C11/419 , G11C7/06 , G11C7/00 , G11C7/02
CPC分类号： G11C7/065
摘要： A device for reading memory cells, wherein the device contains two branches, wherein each branch comprises, connected in cascade, an electronic switch, an active element reactively connected to the active element of the other branch, so as to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element. A microswitch connects the two branches together is inserted between the two active elements.
摘要翻译：一种用于读取存储器单元的装置，其中该装置包含两个分支，其中每个分支包括级联连接的电子开关，与另一分支的有源元件反应地连接的有源元件，以形成电压放大器。每个有源元件通过高阻抗电路元件来控制。将两个分支连接在一起的微动开关插入两个活动元件之间。

6. 发明授权

US5986921A Clock circuit for reading a multilevel non volatile memory cells device 失效
标题翻译：用于读取多级非易失性存储单元器件的时钟电路
公开(公告)号：US5986921A
公开(公告)日：1999-11-16
申请号：US883822
申请日：1997-06-27
申请人： Cristiano Calligaro , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Nicola Telecco , Guido Torelli
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , H03K5/13 , G11C13/00
CPC分类号： H03K5/13 , G11C11/5621 , G11C11/5642 , G11C16/32 , G11C2211/5644
摘要： A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block connected to an input terminal for memory address line transition signals. The delay block drives a counter which feedback controls the discharge through a combinational logic circuit connected to the output terminal of the programmable delay block. A logic output circuit, connected to the output terminal of the delay block and to the counter, generates the timing signals.
摘要翻译：一种用于从包括多级非易失性存储器单元的器件读取的定时电路，该电路包括连接到用于存储器地址线转换信号的输入端的单个可编程延迟块。延迟块驱动计数器，其反馈通过连接到可编程延迟块的输出端的组合逻辑电路来控制放电。连接到延迟块的输出端和计数器的逻辑输出电路产生定时信号。

7. 发明授权

US07317630B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US07317630B2
公开(公告)日：2008-01-08
申请号：US11182374
申请日：2005-07-15
申请人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
发明人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175
摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.
摘要翻译：非易失性存储装置包括单独的控制器电路和存储器电路。控制器电路制造在第一集成电路芯片上。控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

8. 发明授权

US07180276B2 Dual stage voltage regulation circuit 有权
标题翻译：双级电压调节电路
公开(公告)号：US07180276B2
公开(公告)日：2007-02-20
申请号：US11402730
申请日：2006-04-12
申请人： Nicola Telecco
发明人： Nicola Telecco
IPC分类号： G05F1/577
CPC分类号： G05F1/465
摘要： A voltage regulator for supplying two types of loads on a common chip, namely a high current load and a low current load. The voltage regulator employs a feedback loop to supply the low current load with a fine degree of regulation and a feed forward arrangement to supply the high current load with a coarse degree of regulation. The feedback loop employs a bandgap reference source feeding a comparator, with an output driver transistor drawing current from a common supply and having an output electrode connected to a voltage divider, allowing a sample of the output to be fed back to the comparator to maintain the desired output voltage. The output electrode also feeds a control transistor for the feed forward arrangement that also draws current from the common supply and supplies the high current load directly. An example of a single chip circuit employing the present invention is a charge pump where the high current load is a series of large capacitors used to multiply charge to produce a high voltage and the low current load is a plurality of clock circuits that apply timing pulses to switches for proper phasing of the capacitors and associated switches to achieve the desired high voltage.
摘要翻译：用于在公共芯片上提供两种类型负载的电压调节器，即高电流负载和低电流负载。电压调节器采用反馈回路来为低电流负载提供精细的调节程度和前馈布置，以提供粗调节的高电流负载。反馈回路采用馈送比较器的带隙参考源，输出驱动晶体管从公共电源抽取电流，并且具有连接到分压器的输出电极，允许将输出的采样反馈到比较器以保持所需输出电压。输出电极还馈送用于前馈布置的控制晶体管，其也从公共电源吸取电流并直接提供高电流负载。采用本发明的单芯片电路的例子是电荷泵，其中高电流负载是用于乘以电荷以产生高电压的一系列大电容器，并且低电流负载是施加定时脉冲的多个时钟电路以切换电容器和相关开关的适当定相以实现期望的高电压。

9. 发明授权

US07633800B2 Redundancy scheme in memory 有权
标题翻译：内存中的冗余方案
公开(公告)号：US07633800B2
公开(公告)日：2009-12-15
申请号：US11835572
申请日：2007-08-08
申请人： Vijay P. Adusumilli , Nicola Telecco
发明人： Vijay P. Adusumilli , Nicola Telecco
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C29/846
摘要： Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time.
摘要翻译：使用单独的伴随控制器芯片在闪存芯片的外部提供列冗余。伴随芯片最初接收并存储来自FLASH存储器芯片的熔丝地址信息用于闪速存储器中的有缺陷的存储单元。在读取操作模式中，伴随控制芯片检测从FLASH存储器接收到缺陷地址，并存储在从闪速存储器芯片下载的冗余移位寄存器冗余数据中。冗余数据用于向与配套控制芯片接口的外部用户提供正确的FLASH存储器数据。在程序操作模式中，伴随控制芯片提供存储在闪速存储器芯片中的冗余列中的冗余位。伴随的控制芯片通过容易地为位，半字节或字节提供多种不同的冗余方案来提供灵活性，而不需要FLASH存储器芯片本身中的附加逻辑电路。数据在闪存存储器芯片和伴随控制芯片之间一个字节一次传输。

10. 发明授权

US07180779B2 Memory architecture with enhanced over-erase tolerant control gate scheme 有权
标题翻译：具有增强的过擦除宽容控制门控方案的存储架构
公开(公告)号：US07180779B2
公开(公告)日：2007-02-20
申请号：US11178965
申请日：2005-07-11
申请人： Nicola Telecco , Victor Nguyen
发明人： Nicola Telecco , Victor Nguyen
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/26 , G11C16/3477
摘要： The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
摘要翻译：本发明涉及半导体存储器，特别涉及一种减少过度擦除的存储单元的影响或容忍的非易失性或闪速存储器和方法。当存储单元被读取时，读取电压被施加到至少一个目标存储单元，并且低于过擦除存储单元的阈值电压的负偏置电压也被施加到至少一个其他选择的存储单元它与目标存储单元处于同一行。对相邻或邻近的存储器单元施加负偏置电压会关闭附近的单元，以隔离在读取，编程或擦除操作期间来自过擦除的存储单元的电流。

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