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1. 发明授权

US08195735B2 System and method to implement a matrix multiply unit of a broadband processor 失效
标题翻译：实现宽带处理器的矩阵乘法单元的系统和方法
公开(公告)号：US08195735B2
公开(公告)日：2012-06-05
申请号：US12330962
申请日：2008-12-09
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/52 , G06F7/38
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

2. 发明申请

US20090094309A1 SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR 失效
标题翻译：用于实现宽带处理器的矩阵多项式单元的系统和方法
公开(公告)号：US20090094309A1
公开(公告)日：2009-04-09
申请号：US12330962
申请日：2008-12-09
申请人： Craig HANSEN , Bruce Bateman , John Moussouris
发明人： Craig HANSEN , Bruce Bateman , John Moussouris
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

3. 发明授权

US08943119B2 System and method to implement a matrix multiply unit of a broadband processor 有权
标题翻译：实现宽带处理器的矩阵乘法单元的系统和方法
公开(公告)号：US08943119B2
公开(公告)日：2015-01-27
申请号：US13462648
申请日：2012-05-02
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/38 , G06F7/52 , G06F7/533 , G06F7/57 , G06F7/72 , G06F9/30 , G06F17/15 , G06F17/16 , G06F7/48 , G06F7/499
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：一种系统和方法被配置为通过实现一个功能单元来提高通用处理器的性能，该功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的整个资源，而不考虑操作数大小，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

4. 发明申请

US20120215826A1 SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR 有权
标题翻译：用于实现宽带处理器的矩阵多项式单元的系统和方法
公开(公告)号：US20120215826A1
公开(公告)日：2012-08-23
申请号：US13462648
申请日：2012-05-02
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/487 , G06F7/485
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

5. 发明授权

US07483935B2 System and method to implement a matrix multiply unit of a broadband processor 失效
标题翻译：实现宽带处理器的矩阵乘法单元的系统和方法
公开(公告)号：US07483935B2
公开(公告)日：2009-01-27
申请号：US10233779
申请日：2002-09-04
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/00 , G06F7/52
CPC分类号： G06F17/16 , G06F7/5334 , G06F7/724 , G06F9/3001 , G06F9/30036
摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

6. 发明授权

US06378060B1 System to implement a cross-bar switch of a broadband processor 有权
公开(公告)号：US06378060B1
公开(公告)日：2002-04-23
申请号：US09502856
申请日：2000-02-11
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F1300
CPC分类号： G06F13/4022
摘要： The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2n-bit (e.g. 256-bit) input source word to be switched into any bit position of a 2m-bit (e.g. 128-bit) output destination word and (2) provides the ability to set-to-zero any bit in said 2m-bit output destination word. The cross-bar circuit includes: (1) a switch circuit which includes 2m 2n:1 multiplexor circuits, where each of the 2n:1 multiplexor circuits (a) has a unique n-bit (e.g. 8-bit) index input, one disable input, and a 2n-bit wide source input, (b) receives (i) an n-bit index at the n-bit index input, (ii) a disable bit at the disable input, and (iii) the 2n-bit input source word at the 2n-bit wide source input, and (c) decodes the n-bit index either (i) to select and output as an output destination bit one bit from the 2n-bit input source word if the disable bit has a logic low value or (ii) outputs a logic low as the output destination bit if the disable bit has a logic high value; (2) a cache memory that (a) has 2m cache datapath inputs and 2m cache index inputs, (b) receives (i) the datapath information on the 2m cache datapath inputs and (ii) 2m n-bit indexes on the 2m cache index inputs, (c) provides a first set of the n-bit indexes for the switch circuit, and (d) includes a small tightly coupled memory array that stores p (e.g. eight) entries of 2m n-bit indexes for the switch circuit, where the cache memory is logically coupled to the switch circuit; and (3) a control circuit that (a) has a plurality (e.g. 100) of control inputs, (b) receives the partially-decoded instruction information on the plurality of control inputs, (c) provides a second set of the n-bit indexes for the switch circuit, and (d) provides the disable bits for the switch circuit, where the control circuit is logically coupled to the switch circuit and to the cache memory.

7. 发明授权

US08891276B2 Memory array with local bitlines and local-to-global bitline pass gates and gain stages 有权
标题翻译：具有本地位线和本地到全局位线传递门和增益级的存储器阵列
公开(公告)号：US08891276B2
公开(公告)日：2014-11-18
申请号：US13134579
申请日：2011-06-10
申请人： Chang Hua Siau , Bruce Bateman
发明人： Chang Hua Siau , Bruce Bateman
IPC分类号： G11C5/06 , G11C13/00 , G11C16/00 , G11C7/18 , G11C7/00
CPC分类号： G11C5/06 , G11C7/00 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0026 , G11C16/00 , G11C2213/71
摘要： A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.
摘要翻译：存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门和增益级。存储元件形成在字线和本地位线之间。每个本地位线通过相关联的局部到全局位线传递门选择性地耦合到相关联的全局位线。在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线。在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。

8. 发明授权

US08737151B2 Low read current architecture for memory 有权
标题翻译：低读取存储体系结构
公开(公告)号：US08737151B2
公开(公告)日：2014-05-27
申请号：US13252934
申请日：2011-10-04
申请人： Bruce Bateman , Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Bruce Bateman , Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/12 , G11C7/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0045 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
摘要翻译：用于存储器的低读取当前体系结构。允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

9. 发明申请

US20120314468A1 Memory array with local bitlines and local-to-global bitline pass gates and gain stages 有权
标题翻译：具有本地位线和本地到全局位线传递门和增益级的存储器阵列
公开(公告)号：US20120314468A1
公开(公告)日：2012-12-13
申请号：US13134579
申请日：2011-06-10
申请人： Chang Hua Siau , Bruce Bateman
发明人： Chang Hua Siau , Bruce Bateman
IPC分类号： G11C5/06 , G11C5/08 , B82Y10/00
CPC分类号： G11C5/06 , G11C7/00 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0026 , G11C16/00 , G11C2213/71
摘要： A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.
摘要翻译：存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门和增益级。存储元件形成在字线和本地位线之间。每个本地位线通过相关联的局部到全局位线传递门选择性地耦合到相关联的全局位线。在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线。在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。

10. 发明授权

US07800287B2 Enhanced emission from pc-LEDs using IF filters 有权
标题翻译：使用IF滤波器增强pc-LEDs的发射
公开(公告)号：US07800287B2
公开(公告)日：2010-09-21
申请号：US11844713
申请日：2007-08-24
申请人： Yi Zheng , Bruce Bateman , Matthew A. Stough , Madis Raukas
发明人： Yi Zheng , Bruce Bateman , Matthew A. Stough , Madis Raukas
IPC分类号： H01J5/16 , H01J63/04 , F21V9/00
CPC分类号： H01L33/50 , G02B5/28 , H01L33/46
摘要： White-light efficiency from a light emitting diode is enhanced by recycling inwardly penetrating light outwardly by application of a multi-layer, thin film filter between the LED die and the phosphor layer. This procedure increases the package extraction efficiency.
摘要翻译：通过在LED管芯和荧光体层之间施加多层薄膜滤光器，向外再透过向内穿透光来增强来自发光二极管的白光效率。该程序提高了包装提取效率。

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