专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08891276B2 Memory array with local bitlines and local-to-global bitline pass gates and gain stages 有权
标题翻译：具有本地位线和本地到全局位线传递门和增益级的存储器阵列
公开(公告)号：US08891276B2
公开(公告)日：2014-11-18
申请号：US13134579
申请日：2011-06-10
申请人： Chang Hua Siau , Bruce Bateman
发明人： Chang Hua Siau , Bruce Bateman
IPC分类号： G11C5/06 , G11C13/00 , G11C16/00 , G11C7/18 , G11C7/00
CPC分类号： G11C5/06 , G11C7/00 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0026 , G11C16/00 , G11C2213/71
摘要： A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.
摘要翻译：存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门和增益级。存储元件形成在字线和本地位线之间。每个本地位线通过相关联的局部到全局位线传递门选择性地耦合到相关联的全局位线。在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线。在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。

2. 发明授权

US08737151B2 Low read current architecture for memory 有权
标题翻译：低读取存储体系结构
公开(公告)号：US08737151B2
公开(公告)日：2014-05-27
申请号：US13252934
申请日：2011-10-04
申请人： Bruce Bateman , Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Bruce Bateman , Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/12 , G11C7/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0045 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
摘要翻译：用于存储器的低读取当前体系结构。允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

3. 发明申请

US20130043455A1 Vertical Cross Point Arrays For Ultra High Density Memory Applications 有权
标题翻译：用于超高密度存储器应用的垂直交叉点阵列
公开(公告)号：US20130043455A1
公开(公告)日：2013-02-21
申请号：US13210292
申请日：2011-08-15
申请人： BRUCE BATEMAN
发明人： BRUCE BATEMAN
IPC分类号： H01L45/00 , B82Y99/00
CPC分类号： H01L27/249 , H01L27/2418 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
摘要翻译：超高密度垂直交叉点阵列包括多个水平线层，水平线与以行和列排列的多条垂直线交错。垂直线与水平线交错，使得一行垂直线位于每条水平线层中每条连续的一对水平线之间。每个垂直线包括由单层或多层记忆膜包围的中心导体。因此，当与水平线交错时，两端存储单元一体地形成在每条垂直线的中心导体和每个交叉水平线之间。通过配置垂直和水平线，使得一行垂直线位于每条连续的一对水平线之间，可以实现仅仅2F2的单位存储单元占用空间。

4. 发明申请

US20120314468A1 Memory array with local bitlines and local-to-global bitline pass gates and gain stages 有权
标题翻译：具有本地位线和本地到全局位线传递门和增益级的存储器阵列
公开(公告)号：US20120314468A1
公开(公告)日：2012-12-13
申请号：US13134579
申请日：2011-06-10
申请人： Chang Hua Siau , Bruce Bateman
发明人： Chang Hua Siau , Bruce Bateman
IPC分类号： G11C5/06 , G11C5/08 , B82Y10/00
CPC分类号： G11C5/06 , G11C7/00 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0026 , G11C16/00 , G11C2213/71
摘要： A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.
摘要翻译：存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门和增益级。存储元件形成在字线和本地位线之间。每个本地位线通过相关联的局部到全局位线传递门选择性地耦合到相关联的全局位线。在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线。在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。

5. 发明授权

US07800287B2 Enhanced emission from pc-LEDs using IF filters 有权
标题翻译：使用IF滤波器增强pc-LEDs的发射
公开(公告)号：US07800287B2
公开(公告)日：2010-09-21
申请号：US11844713
申请日：2007-08-24
申请人： Yi Zheng , Bruce Bateman , Matthew A. Stough , Madis Raukas
发明人： Yi Zheng , Bruce Bateman , Matthew A. Stough , Madis Raukas
IPC分类号： H01J5/16 , H01J63/04 , F21V9/00
CPC分类号： H01L33/50 , G02B5/28 , H01L33/46
摘要： White-light efficiency from a light emitting diode is enhanced by recycling inwardly penetrating light outwardly by application of a multi-layer, thin film filter between the LED die and the phosphor layer. This procedure increases the package extraction efficiency.
摘要翻译：通过在LED管芯和荧光体层之间施加多层薄膜滤光器，向外再透过向内穿透光来增强来自发光二极管的白光效率。该程序提高了包装提取效率。

6. 发明授权

US08943119B2 System and method to implement a matrix multiply unit of a broadband processor 有权
标题翻译：实现宽带处理器的矩阵乘法单元的系统和方法
公开(公告)号：US08943119B2
公开(公告)日：2015-01-27
申请号：US13462648
申请日：2012-05-02
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/38 , G06F7/52 , G06F7/533 , G06F7/57 , G06F7/72 , G06F9/30 , G06F17/15 , G06F17/16 , G06F7/48 , G06F7/499
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：一种系统和方法被配置为通过实现一个功能单元来提高通用处理器的性能，该功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的整个资源，而不考虑操作数大小，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

7. 发明申请

US20130210211A1 Vertical Cross-Point Memory Arrays 有权
标题翻译：垂直交叉点记忆阵列
公开(公告)号：US20130210211A1
公开(公告)日：2013-08-15
申请号：US13586094
申请日：2012-08-15
申请人： Lidia Vereen , Bruce Bateman , David Eggleston , Louis Parrillo
发明人： Lidia Vereen , Bruce Bateman , David Eggleston , Louis Parrillo
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L23/528 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1616
摘要： A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
摘要翻译：一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和水平线。在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的一对水平线之间。通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。

8. 发明申请

US20130207066A1 PLANAR RESISTIVE MEMORY INTEGRATION 有权
标题翻译：平面电阻记忆整合
公开(公告)号：US20130207066A1
公开(公告)日：2013-08-15
申请号：US13586580
申请日：2012-08-15
申请人： Lidia Vereen , Bruce Bateman , Louis Parrillo , Elizabeth Friend , David Eggleston
发明人： Lidia Vereen , Bruce Bateman , Louis Parrillo , Elizabeth Friend , David Eggleston
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1666 , H01L45/1683
摘要： In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.
摘要翻译：在一个示例中，通过例如提供电介质层，在电介质层中形成空隙，以及形成第一两端电阻存储单元的一部分和第二两端的一部分，形成单个镶嵌结构电阻记忆体在空隙内。两端电阻式存储单元的部分可以垂直地堆叠在空隙内。

9. 发明授权

US08195735B2 System and method to implement a matrix multiply unit of a broadband processor 失效
标题翻译：实现宽带处理器的矩阵乘法单元的系统和方法
公开(公告)号：US08195735B2
公开(公告)日：2012-06-05
申请号：US12330962
申请日：2008-12-09
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/52 , G06F7/38
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

10. 发明申请

US20090094309A1 SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR 失效
标题翻译：用于实现宽带处理器的矩阵多项式单元的系统和方法
公开(公告)号：US20090094309A1
公开(公告)日：2009-04-09
申请号：US12330962
申请日：2008-12-09
申请人： Craig HANSEN , Bruce Bateman , John Moussouris
发明人： Craig HANSEN , Bruce Bateman , John Moussouris
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式